Lines Matching refs:pm4
409 struct si_pm4_state *pm4 = &blend->pm4;
426 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
461 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
472 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
480 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
539 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
572 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
581 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
765 struct si_pm4_state *pm4 = &rs->pm4;
799 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
810 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
821 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
826 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
827 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
834 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
838 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
839 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
851 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
856 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
881 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
883 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
885 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
887 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
889 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1001 struct si_pm4_state *pm4 = &dsa->pm4;
1040 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1046 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1047 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1049 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1050 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
3780 struct si_pm4_state *pm4,
3882 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3886 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3889 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3894 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3898 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3915 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3926 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3928 if (!pm4)
3931 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3932 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3933 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3934 si_pm4_cmd_end(pm4, false);
3936 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3937 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3940 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3941 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3942 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3944 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3945 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3947 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3948 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3950 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3953 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3954 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3956 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4041 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4044 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4047 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4050 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4051 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4052 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4054 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4055 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4058 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4059 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4069 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4070 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4071 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4072 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4073 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4074 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4076 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4077 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4078 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4085 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4089 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4090 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4091 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4092 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4102 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4103 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4110 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4111 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4114 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4120 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4124 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4125 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4140 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4142 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4143 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4147 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4149 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4151 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4152 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4155 si_pm4_upload_indirect_buffer(sctx, pm4);
4156 sctx->init_config = pm4;
