Lines Matching refs:pm4
269 struct si_pm4_state *pm4)
327 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
336 if (shader->pm4)
337 si_pm4_clear_state(shader->pm4);
339 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
341 return shader->pm4;
346 struct si_pm4_state *pm4;
350 pm4 = si_get_shader_pm4_state(shader);
351 if (!pm4)
355 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
361 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
362 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
375 struct si_pm4_state *pm4;
378 pm4 = si_get_shader_pm4_state(shader);
379 if (!pm4)
383 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
385 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
386 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
387 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
392 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
400 struct si_pm4_state *pm4;
406 pm4 = si_get_shader_pm4_state(shader);
407 if (!pm4)
411 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
424 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
426 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
427 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
428 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
434 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
440 si_set_tesseval_regs(sscreen, shader, pm4);
474 struct si_pm4_state *pm4;
479 pm4 = si_get_shader_pm4_state(shader);
480 if (!pm4)
483 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
486 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
489 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
492 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
495 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
500 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
502 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
503 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
504 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
505 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
507 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
512 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
513 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
516 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
521 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
536 struct si_pm4_state *pm4;
545 pm4 = si_get_shader_pm4_state(shader);
546 if (!pm4)
557 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
559 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
561 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
562 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
566 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
582 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
585 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
599 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
600 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
601 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
607 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
617 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
620 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
627 si_set_tesseval_regs(sscreen, shader, pm4);
692 struct si_pm4_state *pm4;
742 pm4 = si_get_shader_pm4_state(shader);
743 if (!pm4)
788 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
789 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
796 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
797 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
799 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
804 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
805 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
808 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
809 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
810 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
812 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
817 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1753 if (shader->pm4) {
1757 si_pm4_delete_state(sctx, ls, shader->pm4);
1759 si_pm4_delete_state(sctx, es, shader->pm4);
1761 si_pm4_delete_state(sctx, vs, shader->pm4);
1764 si_pm4_delete_state(sctx, hs, shader->pm4);
1768 si_pm4_delete_state(sctx, es, shader->pm4);
1770 si_pm4_delete_state(sctx, vs, shader->pm4);
1774 si_pm4_delete_state(sctx, vs, shader->pm4);
1776 si_pm4_delete_state(sctx, gs, shader->pm4);
1779 si_pm4_delete_state(sctx, ps, shader->pm4);
1955 struct si_pm4_state *pm4;
2015 pm4 = CALLOC_STRUCT(si_pm4_state);
2016 if (!pm4)
2021 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2024 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2028 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2031 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2038 sctx->init_config_gs_rings = pm4;
2162 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2168 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2174 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2182 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2184 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2186 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2195 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2197 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2341 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2343 if (!*pm4) {
2346 *pm4 = CALLOC_STRUCT(si_pm4_state);
2364 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2366 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2406 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2413 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2426 sctx->fixed_func_tcs_shader.current->pm4);
2435 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2438 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2446 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2452 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2461 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2462 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2483 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
