Lines Matching refs:sctx
855 static unsigned si_get_alpha_test_func(struct si_context *sctx)
858 if (sctx->queued.named.dsa)
859 return sctx->queued.named.dsa->alpha_func;
864 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
868 struct si_shader_selector *ps = sctx->ps_shader.cso;
871 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
883 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
885 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
886 sctx->queued.named.blend->cb_target_mask;
890 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
921 struct si_context *sctx = (struct si_context *)ctx;
928 if (sctx->vertex_elements) {
930 sctx->vertex_elements->count);
933 sctx->vertex_elements->elements[i].instance_divisor;
936 sctx->vertex_elements->fix_fetch &
939 if (sctx->tes_shader.cso)
941 else if (sctx->gs_shader.cso)
944 si_shader_selector_key_hw_vs(sctx, sel, key);
946 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
952 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
954 if (sel == sctx->fixed_func_tcs_shader.cso)
955 key->mono.tcs.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
958 if (sctx->gs_shader.cso)
961 si_shader_selector_key_hw_vs(sctx, sel, key);
963 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
968 sctx->gs_tri_strip_adj_fix;
971 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
972 struct si_state_blend *blend = sctx->queued.named.blend;
976 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
984 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
986 sctx->framebuffer.spi_shader_col_format_blend) |
988 sctx->framebuffer.spi_shader_col_format_alpha) |
990 sctx->framebuffer.spi_shader_col_format);
999 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1012 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1013 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1014 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1025 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1026 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1027 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1028 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1033 if (sctx->queued.named.blend) {
1034 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1041 sctx->framebuffer.nr_samples <= 1;
1046 sctx->framebuffer.nr_samples > 1 &&
1047 sctx->ps_iter_samples > 1) {
1056 sctx->framebuffer.nr_samples > 1) {
1078 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1251 struct si_context *sctx = (struct si_context *)ctx;
1255 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1459 struct si_context *sctx = (struct si_context*)ctx;
1467 sel->compiler_ctx_state.tm = sctx->tm;
1468 sel->compiler_ctx_state.debug = sctx->b.debug;
1469 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1644 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1645 sctx->is_debug ||
1659 struct si_context *sctx = (struct si_context *)ctx;
1662 if (sctx->vs_shader.cso == sel)
1665 sctx->vs_shader.cso = sel;
1666 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1667 sctx->do_update_shaders = true;
1668 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1669 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1674 struct si_context *sctx = (struct si_context *)ctx;
1676 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1678 if (sctx->gs_shader.cso == sel)
1681 sctx->gs_shader.cso = sel;
1682 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1683 sctx->do_update_shaders = true;
1684 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1685 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1688 si_shader_change_notify(sctx);
1689 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1694 struct si_context *sctx = (struct si_context *)ctx;
1696 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1698 if (sctx->tcs_shader.cso == sel)
1701 sctx->tcs_shader.cso = sel;
1702 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1703 sctx->do_update_shaders = true;
1706 sctx->last_tcs = NULL; /* invalidate derived tess state */
1711 struct si_context *sctx = (struct si_context *)ctx;
1713 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1715 if (sctx->tes_shader.cso == sel)
1718 sctx->tes_shader.cso = sel;
1719 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1720 sctx->do_update_shaders = true;
1721 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1722 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1725 si_shader_change_notify(sctx);
1726 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1728 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1733 struct si_context *sctx = (struct si_context *)ctx;
1737 if (sctx->ps_shader.cso == sel)
1740 sctx->ps_shader.cso = sel;
1741 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1742 sctx->do_update_shaders = true;
1743 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1746 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1757 si_pm4_delete_state(sctx, ls, shader->pm4);
1759 si_pm4_delete_state(sctx, es, shader->pm4);
1761 si_pm4_delete_state(sctx, vs, shader->pm4);
1764 si_pm4_delete_state(sctx, hs, shader->pm4);
1768 si_pm4_delete_state(sctx, es, shader->pm4);
1770 si_pm4_delete_state(sctx, vs, shader->pm4);
1774 si_pm4_delete_state(sctx, vs, shader->pm4);
1776 si_pm4_delete_state(sctx, gs, shader->pm4);
1779 si_pm4_delete_state(sctx, ps, shader->pm4);
1790 struct si_context *sctx = (struct si_context *)ctx;
1794 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1795 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1796 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1797 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1798 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1810 si_delete_shader(sctx, p);
1815 si_delete_shader(sctx, sel->main_shader_part);
1817 si_delete_shader(sctx, sel->gs_copy_shader);
1825 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1833 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1838 sctx->sprite_coord_enable & (1 << index))) {
1883 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1885 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1886 struct si_shader *ps = sctx->ps_shader.current;
1887 struct si_shader *vs = si_get_vs_state(sctx);
1903 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1920 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1931 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1933 if (sctx->init_config_has_vgt_flush)
1937 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1938 si_pm4_cmd_add(sctx->init_config,
1940 si_pm4_cmd_end(sctx->init_config, false);
1943 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1944 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1945 si_pm4_cmd_end(sctx->init_config, false);
1946 sctx->init_config_has_vgt_flush = true;
1950 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1953 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1954 struct si_shader_selector *gs = sctx->gs_shader.cso;
1958 unsigned num_se = sctx->screen->b.info.max_se;
1987 (!sctx->esgs_ring ||
1988 sctx->esgs_ring->width0 < esgs_ring_size);
1990 (!sctx->gsvs_ring ||
1991 sctx->gsvs_ring->width0 < gsvs_ring_size);
1997 pipe_resource_reference(&sctx->esgs_ring, NULL);
1998 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2001 if (!sctx->esgs_ring)
2006 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2007 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2010 if (!sctx->gsvs_ring)
2019 if (sctx->b.chip_class >= CIK) {
2020 if (sctx->esgs_ring)
2022 sctx->esgs_ring->width0 / 256);
2023 if (sctx->gsvs_ring)
2025 sctx->gsvs_ring->width0 / 256);
2027 if (sctx->esgs_ring)
2029 sctx->esgs_ring->width0 / 256);
2030 if (sctx->gsvs_ring)
2032 sctx->gsvs_ring->width0 / 256);
2036 if (sctx->init_config_gs_rings)
2037 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2038 sctx->init_config_gs_rings = pm4;
2040 if (!sctx->init_config_has_vgt_flush) {
2041 si_init_config_add_vgt_flush(sctx);
2042 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2046 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2047 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2050 if (sctx->esgs_ring) {
2051 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2052 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2054 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2055 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2058 if (sctx->gsvs_ring) {
2059 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2060 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2072 static int si_update_scratch_buffer(struct si_context *sctx,
2075 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2087 if (shader->scratch_bo == sctx->scratch_buffer)
2090 assert(sctx->scratch_buffer);
2092 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2095 r = si_shader_binary_upload(sctx->screen, shader);
2100 si_shader_init_pm4_state(sctx->screen, shader);
2102 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2107 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2109 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2117 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2121 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2122 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2123 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2124 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2125 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2129 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2132 si_get_current_scratch_buffer_size(sctx);
2134 si_get_max_scratch_bytes_per_wave(sctx);
2136 sctx->scratch_waves;
2143 r600_resource_reference(&sctx->scratch_buffer, NULL);
2145 sctx->scratch_buffer = (struct r600_resource*)
2146 pipe_buffer_create(&sctx->screen->b.b, 0,
2148 if (!sctx->scratch_buffer)
2150 sctx->emit_scratch_reloc = true;
2158 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2162 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2164 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2168 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2170 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2174 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2177 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2181 if (sctx->tes_shader.current)
2182 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2183 else if (sctx->gs_shader.current)
2184 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2186 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2190 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2194 if (sctx->gs_shader.current)
2195 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2197 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2205 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2207 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2208 sctx->spi_tmpring_size = spi_tmpring_size;
2209 sctx->emit_scratch_reloc = true;
2214 static void si_init_tess_factor_ring(struct si_context *sctx)
2216 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2217 sctx->b.family != CHIP_CARRIZO &&
2218 sctx->b.family != CHIP_STONEY;
2221 sctx->screen->b.info.max_se;
2224 switch (sctx->screen->tess_offchip_block_dw_size) {
2236 switch (sctx->b.chip_class) {
2249 assert(!sctx->tf_ring);
2250 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2252 32768 * sctx->screen->b.info.max_se);
2253 if (!sctx->tf_ring)
2256 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2258 sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2261 sctx->screen->tess_offchip_block_dw_size * 4);
2262 if (!sctx->tess_offchip_ring)
2265 si_init_config_add_vgt_flush(sctx);
2268 if (sctx->b.chip_class >= CIK) {
2269 if (sctx->b.chip_class >= VI)
2272 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2273 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2274 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2275 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2276 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2281 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2282 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2283 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2284 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2285 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2292 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2293 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2294 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2296 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2297 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2299 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2300 sctx->tess_offchip_ring, 0,
2301 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2309 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2318 assert(!sctx->fixed_func_tcs_shader.cso);
2332 sctx->fixed_func_tcs_shader.cso =
2333 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2336 static void si_update_vgt_shader_config(struct si_context *sctx)
2340 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2341 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2348 if (sctx->tes_shader.cso) {
2352 if (sctx->gs_shader.cso)
2358 } else if (sctx->gs_shader.cso) {
2366 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2369 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2377 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2378 sctx->b.streamout.stride_in_dw = shader->so.stride;
2381 bool si_update_shaders(struct si_context *sctx)
2383 struct pipe_context *ctx = (struct pipe_context*)sctx;
2385 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2386 struct si_shader *old_vs = si_get_vs_state(sctx);
2390 compiler_state.tm = sctx->tm;
2391 compiler_state.debug = sctx->b.debug;
2392 compiler_state.is_debug_context = sctx->is_debug;
2395 if (sctx->tes_shader.cso) {
2396 if (!sctx->tf_ring) {
2397 si_init_tess_factor_ring(sctx);
2398 if (!sctx->tf_ring)
2403 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2406 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2408 if (sctx->tcs_shader.cso) {
2409 r = si_shader_select(ctx, &sctx->tcs_shader,
2413 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2415 if (!sctx->fixed_func_tcs_shader.cso) {
2416 si_generate_fixed_func_tcs(sctx);
2417 if (!sctx->fixed_func_tcs_shader.cso)
2421 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
2425 si_pm4_bind_state(sctx, hs,
2426 sctx->fixed_func_tcs_shader.current->pm4);
2429 r = si_shader_select(ctx, &sctx->tes_shader, &compiler_state);
2433 if (sctx->gs_shader.cso) {
2435 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2438 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2439 si_update_so(sctx, sctx->tes_shader.cso);
2441 } else if (sctx->gs_shader.cso) {
2443 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2446 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2449 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2452 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2453 si_update_so(sctx, sctx->vs_shader.cso);
2457 if (sctx->gs_shader.cso) {
2458 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
2461 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2462 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2463 si_update_so(sctx, sctx->gs_shader.cso);
2465 if (!si_update_gs_ring_buffers(sctx))
2468 si_pm4_bind_state(sctx, gs, NULL);
2469 si_pm4_bind_state(sctx, es, NULL);
2472 si_update_vgt_shader_config(sctx);
2474 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
2475 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2477 if (sctx->ps_shader.cso) {
2480 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
2483 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2486 sctx->ps_shader.cso->db_shader_control |
2487 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2489 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2490 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2491 sctx->flatshade != rs->flatshade) {
2492 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2493 sctx->flatshade = rs->flatshade;
2494 si_mark_atom_dirty(sctx, &sctx->spi_map);
2497 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2498 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2500 if (sctx->ps_db_shader_control != db_shader_control) {
2501 sctx->ps_db_shader_control = db_shader_control;
2502 si_mark_atom_dirty(sctx, &sctx
2505 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
2506 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
2507 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2509 if (sctx->b.chip_class == SI)
2510 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2512 if (sctx->framebuffer.nr_samples <= 1)
2513 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2517 if (si_pm4_state_changed(sctx, ls) ||
2518 si_pm4_state_changed(sctx, hs) ||
2519 si_pm4_state_changed(sctx, es) ||
2520 si_pm4_state_changed(sctx, gs) ||
2521 si_pm4_state_changed(sctx, vs) ||
2522 si_pm4_state_changed(sctx, ps)) {
2523 if (!si_update_spi_tmpring_size(sctx))
2527 sctx->do_update_shaders = false;
2531 void si_init_shader_functions(struct si_context *sctx)
2533 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2535 sctx->b.b.create_vs_state = si_create_shader_selector;
2536 sctx->b.b.create_tcs_state = si_create_shader_selector;
2537 sctx->b.b.create_tes_state = si_create_shader_selector;
2538 sctx->b.b.create_gs_state = si_create_shader_selector;
2539 sctx->b.b.create_fs_state = si_create_shader_selector;
2541 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2542 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2543 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2544 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2545 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2547 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2548 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2549 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2550 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2551 sctx->b.b.delete_fs_state = si_delete_shader_selector;
