Lines Matching refs:rrb
52 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
55 "%s(rb %p, rrb %p) \n",
56 __func__, rb, rrb);
58 assert(rrb);
60 if (rrb && rrb->bo) {
61 radeon_bo_unref(rrb->bo);
67 static GLuint get_depth_z32(const struct radeon_renderbuffer * rrb,
72 ba = (y >> 4) * (rrb->pitch >> 6) + (x >> 4);
84 static GLuint get_depth_z16(const struct radeon_renderbuffer * rrb,
89 ba = (y / 16) * (rrb->pitch >> 6) + (x / 32);
103 static GLuint get_depth_z32(const struct radeon_renderbuffer * rrb,
109 b = (((y & 0x7ff) >> 4) * (rrb->pitch >> 7) + (x >> 5));
111 offset += (((rrb->pitch >> 7) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
123 static GLuint get_depth_z16(const struct radeon_renderbuffer *rrb,
130 b = (((y >> 4) * (rrb->pitch >> 7) + (x >> 6)));
132 offset += (((rrb->pitch >> 7) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
154 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
159 uint32_t pitch = w * rrb->cpp;
161 rrb->map_pitch = pitch;
163 rrb->map_buffer = malloc(w * h * 4);
164 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
167 untiled_s8z24_map = rrb->map_buffer;
168 tiled_s8z24_map = rrb->bo->ptr;
173 uint32_t src_offset = get_depth_z32(rrb, x + pix_x, flipped_y);
174 uint32_t dst_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
179 radeon_bo_unmap(rrb->bo);
181 *out_map = rrb->map_buffer;
182 *out_stride = rrb->map_pitch;
193 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
198 uint32_t pitch = w * rrb->cpp;
200 rrb->map_pitch = pitch;
202 rrb->map_buffer = malloc(w * h * 2);
203 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
207 untiled_z16_map = rrb->map_buffer;
208 tiled_z16_map = rrb->bo->ptr;
213 uint32_t src_offset = get_depth_z16(rrb, x + pix_x, flipped_y);
214 uint32_t dst_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
219 radeon_bo_unmap(rrb->bo);
221 *out_map = rrb->map_buffer;
222 *out_stride = rrb->map_pitch;
234 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
241 if (!rrb || !rrb->bo) {
247 rrb->map_mode = mode;
248 rrb->map_x = x;
249 rrb->map_y = y;
250 rrb->map_w = w;
251 rrb->map_h = h;
252 rrb->map_pitch = rrb->pitch;
254 ok = rmesa->vtbl.check_blit(rb->Format, rrb->pitch / rrb->cpp);
261 src_y = rrb->base.Base.Height - y - h;
269 rrb->map_pitch = rrb->pitch;
271 assert(!rrb->map_bo);
272 rrb->map_bo = radeon_bo_open(rmesa->radeonScreen->bom, 0,
273 rrb->map_pitch * h, 4,
276 ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset,
277 rb->Format, rrb->pitch / rrb->cpp,
280 rrb->map_bo, 0,
281 rb->Format, rrb->map_pitch / rrb->cpp,
288 ret = radeon_bo_map(rrb->map_bo, !!(mode & GL_MAP_WRITE_BIT));
291 map = rrb->map_bo->ptr;
295 *out_stride = rrb->map_pitch;
297 *out_map = map + (h - 1) * rrb->map_pitch;
298 *out_stride = -rrb->map_pitch;
304 if (radeon_bo_is_referenced_by_cs(rrb->bo, rmesa->cmdbuf.cs)) {
308 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) {
321 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
325 map = rrb->bo->ptr;
326 stride = rrb->map_pitch;
333 map += rrb->draw_offset;
336 map += x * rrb->cpp;
347 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
349 if (!rrb->map_buffer)
352 if (rrb->map_mode & GL_MAP_WRITE_BIT) {
353 uint32_t *untiled_s8z24_map = rrb->map_buffer;
358 radeon_bo_map(rrb->bo, 1);
360 tiled_s8z24_map = rrb->bo->ptr;
362 for (uint32_t pix_y = 0; pix_y < rrb->map_h; pix_y++) {
363 for (uint32_t pix_x = 0; pix_x < rrb->map_w; pix_x++) {
364 uint32_t flipped_y = y_flip * (int32_t)(pix_y + rrb->map_y) + y_bias;
365 uint32_t dst_offset = get_depth_z32(rrb, rrb->map_x + pix_x, flipped_y);
366 uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
370 radeon_bo_unmap(rrb->bo);
372 free(rrb->map_buffer);
373 rrb->map_buffer = NULL;
380 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
382 if (!rrb->map_buffer)
385 if (rrb->map_mode & GL_MAP_WRITE_BIT) {
386 uint16_t *untiled_z16_map = rrb->map_buffer;
391 radeon_bo_map(rrb->bo, 1);
393 tiled_z16_map = rrb->bo->ptr;
395 for (uint32_t pix_y = 0; pix_y < rrb->map_h; pix_y++) {
396 for (uint32_t pix_x = 0; pix_x < rrb->map_w; pix_x++) {
397 uint32_t flipped_y = y_flip * (int32_t)(pix_y + rrb->map_y) + y_bias;
398 uint32_t dst_offset = get_depth_z16(rrb, rrb->map_x + pix_x, flipped_y);
399 uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp;
403 radeon_bo_unmap(rrb->bo);
405 free(rrb->map_buffer);
406 rrb->map_buffer = NULL;
415 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
417 if ((rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_DEPTH_ALWAYS_TILED) && !rrb->has_surface) {
428 if (!rrb->map_bo) {
429 if (rrb->bo)
430 radeon_bo_unmap(rrb->bo);
434 radeon_bo_unmap(rrb->map_bo);
436 if (rrb->map_mode & GL_MAP_WRITE_BIT) {
438 ok = rmesa->vtbl.blit(ctx, rrb->map_bo, 0,
439 rb->Format, rrb->map_pitch / rrb->cpp,
440 rrb->map_w, rrb->map_h,
442 rrb->bo, rrb->draw_offset,
443 rb->Format, rrb->pitch / rrb->cpp,
445 rrb->map_x, rrb->map_y,
446 rrb->map_w, rrb->map_h,
452 radeon_bo_unref(rrb->map_bo);
453 rrb->map_bo = NULL;
467 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
537 if (rrb->bo)
538 radeon_bo_unref(rrb->bo);
547 rrb->pitch = pitch * cpp;
548 rrb->cpp = cpp;
549 rrb->bo = radeon_bo_open(radeon->radeonScreen->bom,
566 struct radeon_renderbuffer *rrb;
576 rrb = radeon_renderbuffer(rb);
581 if (rrb->bo)
582 radeon_bo_unref(rrb->bo);
583 rrb->bo = image->bo;
584 radeon_bo_ref(rrb->bo);
588 rrb->cpp = image->cpp;
589 rrb->pitch = image->pitch * image->cpp;
639 struct radeon_renderbuffer *rrb;
642 rrb = CALLOC_STRUCT(radeon_renderbuffer);
645 "%s( rrb %p ) \n",
646 __func__, rrb);
648 if (!rrb)
651 rb = &rrb->base.Base;
659 rrb->dPriv = driDrawPriv;
664 rrb->bo = NULL;
665 return rrb;
671 struct radeon_renderbuffer *rrb;
675 rrb = CALLOC_STRUCT(radeon_renderbuffer);
678 "%s(%p, rrb %p) \n",
679 __func__, ctx, rrb);
681 if (!rrb)
684 rb = &rrb->base.Base;
729 radeon_update_wrapper(struct gl_context *ctx, struct radeon_renderbuffer *rrb,
732 struct gl_renderbuffer *rb = &rrb->base.Base;
735 "%s(%p, rrb %p, texImage %p, texFormat %s) \n",
736 __func__, ctx, rrb, texImage, _mesa_get_format_name(texImage->TexFormat));
738 rrb->cpp = _mesa_get_format_bytes(texImage->TexFormat);
739 rrb->pitch = texImage->Width * rrb->cpp;
758 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
763 "%s(%p, fb %p, rrb %p, att %p)\n",
764 __func__, ctx, fb, rrb, att);
779 if (!radeon_update_wrapper(ctx, rrb, newImage)) {
789 if (rrb->bo != radeon_image->mt->bo) {
790 if (rrb->bo)
791 radeon_bo_unref(rrb->bo);
792 rrb->bo = radeon_image->mt->bo;
793 radeon_bo_ref(rrb->bo);
809 rrb->draw_offset = imageOffset;
810 rrb->pitch = radeon_image->mt->levels[att->TextureLevel].rowstride;
