Lines Matching refs:hw
517 rmesa->radeon.hw.max_state_size = 0;
521 rmesa->hw.ATOM.cmd_size = SZ; \
522 rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \
523 rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \
524 rmesa->hw.ATOM.name = NM; \
525 rmesa->hw.ATOM.is_tcl = FLAG; \
526 rmesa->hw.ATOM.check = check_##CHK; \
527 rmesa->hw.ATOM.dirty = GL_TRUE; \
528 rmesa->hw.ATOM.idx = IDX; \
529 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
538 rmesa->hw.ctx.emit = ctx_emit_cs;
539 rmesa->hw.ctx.check = check_always_ctx;
578 rmesa->hw.tex[i].emit = tex_emit_cs;
584 rmesa->hw.cube[i].emit = cube_emit_cs;
594 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
595 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
596 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
597 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
598 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
599 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
600 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
601 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
602 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
603 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
604 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
605 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
606 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
607 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
608 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
609 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
610 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
611 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
612 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
613 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
614 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
615 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
616 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
617 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
618 rmesa->hw.mtl.cmd[MTL_CMD_0] =
620 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
621 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
622 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
623 rmesa->hw.grd.cmd[GRD_CMD_0] =
625 rmesa->hw.fog.cmd[FOG_CMD_0] =
627 rmesa->hw.glt.cmd[GLT_CMD_0] =
629 rmesa->hw.eye.cmd[EYE_CMD_0] =
633 rmesa->hw.mat[i].cmd[MAT_CMD_0] =
638 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
640 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
645 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
649 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
650 rmesa->hw.stp.cmd[STP_DATA_0] = 0;
651 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
653 rmesa->hw.grd.emit = scl_emit;
654 rmesa->hw.fog.emit = vec_emit;
655 rmesa->hw.glt.emit = vec_emit;
656 rmesa->hw.eye.emit = vec_emit;
658 rmesa->hw.mat[i].emit = vec_emit;
661 rmesa->hw.lit[i].emit = lit_emit;
664 rmesa->hw.ucp[i].emit = vec_emit;
668 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
675 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
679 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
681 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
685 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
693 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
697 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
699 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
703 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
706 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
711 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
714 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
724 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
726 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
729 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
744 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
752 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
755 rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
760 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
762 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
766 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
768 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
773 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
774 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
776 rmesa->hw.msc.cmd[MSC_RE_MISC] =
781 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
782 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
783 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
784 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
785 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
786 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
789 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
790 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
798 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
801 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
802 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
809 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
816 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
818 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
819 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
821 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
823 hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
825 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
827 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
834 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
840 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
848 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
852 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
858 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
862 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
864 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
876 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
891 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
910 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
911 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
912 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
913 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
915 rmesa->hw.eye.cmd[EYE_X] = 0;
916 rmesa->hw.eye.cmd[EYE_Y] = 0;
917 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
918 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
924 rmesa->radeon.hw.all_dirty = GL_TRUE;
