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Lines Matching refs:addPred

282           DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
293 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias));
331 UseSU->addPred(dep);
344 UseSU->addPred(dep);
374 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
429 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
434 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
440 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
447 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
450 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
453 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
458 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
475 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
491 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency,
499 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
502 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
506 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
515 ExitSU.addPred(SDep(SU, SDep::Order, 0,
533 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
544 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
552 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
554 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));