Lines Matching refs:Ctlz
1073 case ISD::CTLZ: return visitCTLZ(N);
3602 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3603 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3613 // If all of the bits input the to ctlz node are known to be zero, then
3614 // the result of the ctlz is "32" and the result of the shift is one.
3618 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3621 // could be set on input to the CTLZ node. If this bit is set, the SRL
3622 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3710 // fold (ctlz c1) -> c2
3712 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
7646 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7649 TLI.isOperationLegal(ISD::CTLZ, XType))) {
7650 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7651 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7653 getShiftAmountTy(Ctlz.getValueType())));
