Lines Matching refs:ResultReg
176 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
190 unsigned &ResultReg);
280 unsigned ResultReg = createResultReg(RC);
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
284 return ResultReg;
290 unsigned ResultReg = createResultReg(RC);
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
300 TII.get(TargetOpcode::COPY), ResultReg)
303 return ResultReg;
310 unsigned ResultReg = createResultReg(RC);
314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
322 TII.get(TargetOpcode::COPY), ResultReg)
325 return ResultReg;
333 unsigned ResultReg = createResultReg(RC);
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
347 TII.get(TargetOpcode::COPY), ResultReg)
350 return ResultReg;
357 unsigned ResultReg = createResultReg(RC);
361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
369 TII.get(TargetOpcode::COPY), ResultReg)
372 return ResultReg;
379 unsigned ResultReg = createResultReg(RC);
383 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
391 TII.get(TargetOpcode::COPY), ResultReg)
394 return ResultReg;
402 unsigned ResultReg = createResultReg(RC);
406 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
416 TII.get(TargetOpcode::COPY), ResultReg)
419 return ResultReg;
425 unsigned ResultReg = createResultReg(RC);
429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
435 TII.get(TargetOpcode::COPY), ResultReg)
438 return ResultReg;
444 unsigned ResultReg = createResultReg(RC);
448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
455 ResultReg)
458 return ResultReg;
464 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
468 DL, TII.get(TargetOpcode::COPY), ResultReg)
470 return ResultReg;
673 unsigned ResultReg = createResultReg(RC);
676 TII.get(Opc), ResultReg)
679 return ResultReg;
859 unsigned ResultReg = createResultReg(RC);
862 TII.get(Opc), ResultReg)
865 Addr.Base.Reg = ResultReg;
917 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
950 ResultReg = createResultReg(RC);
952 TII.get(Opc), ResultReg);
971 unsigned ResultReg;
972 if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
973 UpdateValueMap(I, ResultReg);
1350 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1352 ResultReg)
1354 UpdateValueMap(I, ResultReg);
1377 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1379 ResultReg)
1384 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1410 unsigned ResultReg = createResultReg(RC);
1412 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1415 UpdateValueMap(I, ResultReg);
1501 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1503 TII.get(Opc), ResultReg)
1505 UpdateValueMap(I, ResultReg);
1512 EVT SrcVT, unsigned &ResultReg) {
1517 ResultReg = RR;
1689 unsigned ResultReg = createResultReg(DstRC);
1691 TII.get(ARM::VMOVDRR), ResultReg)
1699 UpdateValueMap(I, ResultReg);
1705 unsigned ResultReg = createResultReg(DstRC);
1707 ResultReg).addReg(RVLocs[0].getLocReg());
1711 UpdateValueMap(I, ResultReg);
