Lines Matching refs:PredReg
92 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
104 unsigned PredReg,
110 ARMCC::CondCodes Pred, unsigned PredReg,
293 unsigned PredReg, unsigned Scratch, DebugLoc dl,
346 .addImm(Pred).addReg(PredReg).addReg(0);
357 .addImm(Pred).addReg(PredReg);
373 ARMCC::CondCodes Pred, unsigned PredReg,
408 Pred, PredReg, Scratch, dl, Regs))
440 ARMCC::CondCodes Pred, unsigned PredReg,
493 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
494 MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
505 Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
511 ARMCC::CondCodes Pred, unsigned PredReg){
529 MyPredReg == PredReg);
534 ARMCC::CondCodes Pred, unsigned PredReg){
552 MyPredReg == PredReg);
688 unsigned PredReg = 0;
689 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
709 isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
713 isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
728 isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
731 isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
750 .addImm(Pred).addReg(PredReg);
843 unsigned PredReg = 0;
844 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
857 if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) {
861 isMatchingIncrement(PrevMBBI, Base, Bytes, Limit,Pred,PredReg)) {
877 isMatchingDecrement(NextMBBI, Base, Bytes, Limit, Pred, PredReg)) {
880 } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Limit,Pred,PredReg)) {
905 .addImm(Pred).addReg(PredReg)
915 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
920 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
927 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
939 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
945 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1051 ARMCC::CondCodes Pred, unsigned PredReg,
1058 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1064 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1097 unsigned PredReg = 0;
1098 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
1109 .addImm(Pred).addReg(PredReg)
1116 .addImm(Pred).addReg(PredReg)
1139 Pred, PredReg, TII, isT2);
1144 Pred, PredReg, TII, isT2);
1156 Pred, PredReg, TII, isT2);
1161 Pred, PredReg, TII, isT2);
1208 unsigned PredReg = 0;
1209 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MBBI, PredReg);
1227 CurrPredReg = PredReg;
1238 // No need to match PredReg.
1427 unsigned &PredReg, ARMCC::CondCodes &Pred,
1506 int &Offset, unsigned &PredReg,
1568 Pred = llvm::getInstrPredicate(Op0, PredReg);
1666 unsigned BaseReg = 0, PredReg = 0;
1674 Offset, PredReg, Pred, isT2)) {
1694 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1706 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1760 unsigned PredReg = 0;
1761 if (llvm::getInstrPredicate(MI, PredReg) != ARMCC::AL)
