Lines Matching refs:ee
72 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
81 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
87 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
102 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
129 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
132 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
141 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
142 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
145 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
146 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
152 ee->ee_is_hb63 = 1;
154 ee->ee_is_hb63 = 0;
157 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
158 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? 1 : 0;
170 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
176 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
177 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
178 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
181 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
182 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
183 ee->ee_ant_control[mode][i++] = val & 0x3f;
186 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
187 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
188 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
191 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
192 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
193 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
194 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
197 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
198 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
199 ee->ee_ant_control[mode][i++] = val & 0x3f;
203 (ee->ee_ant_control[mode][0] << 4);
205 ee->ee_ant_control[mode][1] |
206 (ee->ee_ant_control[mode][2] << 6) |
207 (ee->ee_ant_control[mode][3] << 12) |
208 (ee->ee_ant_control[mode][4] << 18) |
209 (ee->ee_ant_control[mode][5] << 24);
211 ee->ee_ant_control[mode][6] |
212 (ee->ee_ant_control[mode][7] << 6) |
213 (ee->ee_ant_control[mode][8] << 12) |
214 (ee->ee_ant_control[mode][9] << 18) |
215 (ee->ee_ant_control[mode][10] << 24);
230 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
235 ee->ee_n_piers[mode] = 0;
237 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
240 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
241 ee->ee_db[mode][3] = (val >> 2) & 0x7;
242 ee->ee_ob[mode][2] = (val << 1) & 0x7;
245 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
246 ee->ee_db[mode][2] = (val >> 12) & 0x7;
247 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
248 ee->ee_db[mode][1] = (val >> 6) & 0x7;
249 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
250 ee->ee_db[mode][0] = val & 0x7;
254 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
255 ee->ee_db[mode][1] = val & 0x7;
260 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
261 ee->ee_thr_62[mode] = val & 0xff;
264 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
267 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
268 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
271 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
274 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
276 ee->ee_noise_floor_thr[mode] = val & 0xff;
279 ee->ee_noise_floor_thr[mode] =
283 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
284 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
285 ee->ee_xpd[mode] = val & 0x1;
288 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
292 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
295 ee->ee_xr_power[mode] = val & 0x3f;
297 ee->ee_ob[mode][0] = val & 0x7;
298 ee->ee_db[mode][0] = (val >> 3) & 0x7;
303 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
304 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
306 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
309 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
312 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
314 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
320 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
321 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
336 ee->ee_margin_tx_rx[mode] = val & 0x3f;
341 ee->ee_pwr_cal_b[0].freq =
342 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
343 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
344 ee->ee_n_piers[mode]++;
346 ee->ee_pwr_cal_b[1].freq =
347 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
348 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
349 ee->ee_n_piers[mode]++;
352 ee->ee_pwr_cal_b[2].freq =
353 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
354 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
355 ee->ee_n_piers[mode]++;
358 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
363 ee->ee_pwr_cal_g[0].freq =
364 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
365 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
366 ee->ee_n_piers[mode]++;
368 ee->ee_pwr_cal_g[1].freq =
369 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
370 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
371 ee->ee_n_piers[mode]++;
374 ee->ee_turbo_max_power[mode] = val & 0x7f;
375 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
378 ee->ee_pwr_cal_g[2].freq =
379 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
380 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
381 ee->ee_n_piers[mode]++;
384 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
387 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
388 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
392 ee->ee_cck_ofdm_gain_delta = val & 0xff;
411 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
416 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
421 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
423 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
425 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
426 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
428 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
430 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
431 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
433 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
434 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
437 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
439 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
441 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
442 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
444 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
446 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
447 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
461 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
474 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
475 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
495 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
496 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
497 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
509 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
516 ee->ee_n_piers[mode] = 0;
524 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
526 ee->ee_n_piers[mode]++;
532 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
534 ee->ee_n_piers[mode]++;
547 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
548 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
553 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
585 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
588 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
600 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
605 pcal = ee->ee_pwr_cal_b;
608 pcal = ee->ee_pwr_cal_g;
666 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
670 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
673 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
691 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
697 ee->ee_pd_gains[mode] = 1;
737 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
743 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
746 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
755 pcal = ee->ee_pwr_cal_a;
758 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
759 !AR5K_EEPROM_HDR_11G(ee->ee_header))
762 pcal = ee->ee_pwr_cal_b;
769 ee->ee_n_piers[mode] = 3;
772 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
775 pcal = ee->ee_pwr_cal_g;
782 ee->ee_n_piers[mode] = 3;
788 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
847 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
849 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
853 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
866 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
952 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
955 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
969 if ((ee->ee_x_gain[mode] >> i) & 0x1)
972 ee->ee_pd_gains[mode] = pd_gains;
982 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
986 gen_chan_info = ee->ee_pwr_cal_a;
989 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
990 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
994 gen_chan_info = ee->ee_pwr_cal_b;
997 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
998 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1000 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1004 gen_chan_info = ee->ee_pwr_cal_g;
1010 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1047 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
1086 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1091 sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1092 sz *= ee->ee_n_piers[mode];
1100 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1102 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1106 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1107 offset += ath5k_pdgains_size_2413(ee,
1112 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1113 offset += ath5k_pdgains_size_2413(ee,
1132 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1134 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1139 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1152 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1160 if (pdg == ee->ee_pd_gains[mode] - 1)
1197 if (pdg == ee->ee_pd_gains[mode] - 1)
1210 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1213 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1226 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1230 ee->ee_pd_gains[mode] = pd_gains;
1235 offset = ath5k_cal_data_offset_2413(ee, mode);
1238 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1243 chinfo = ee->ee_pwr_cal_a;
1246 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1251 chinfo = ee->ee_pwr_cal_b;
1254 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1259 chinfo = ee->ee_pwr_cal_g;
1265 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1401 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1408 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1409 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1412 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1413 rate_pcal_info = ee->ee_rate_tpwr_a;
1414 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1417 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1418 rate_pcal_info = ee->ee_rate_tpwr_b;
1419 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1422 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1423 rate_pcal_info = ee->ee_rate_tpwr_g;
1424 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1431 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1435 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1456 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1495 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1501 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1504 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1527 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1533 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1535 chinfo = ee->ee_pwr_cal_a;
1538 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1540 chinfo = ee->ee_pwr_cal_b;
1543 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1545 chinfo = ee->ee_pwr_cal_g;
1551 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1555 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1584 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1593 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1594 offset = AR5K_EEPROM_CTL(ee->ee_version);
1595 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1596 for (i = 0; i < ee->ee_ctls; i += 2) {
1598 ee->ee_ctl[i] = (val >> 8) & 0xff;
1599 ee->ee_ctl[i + 1] = val & 0xff;
1603 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1604 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1607 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1609 rep = ee->ee_ctl_pwr;
1610 for(i = 0; i < ee->ee_ctls; i++) {
1611 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1620 if (ee->ee_ctl[i] == 0) {
1621 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1628 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1679 rep[j].freq = ath5k_eeprom_bin2freq(ee,
