Lines Matching defs:in
119 /* Extended bits are in bits 8 and 9 of MII_CTRL1000 */
136 /* Extended bits are in bits 10 and 11 of MII_STAT1000 */
224 /* Bits in MMDREG_CTRL1 */
229 /* Bits in MMDREG_STAT1 */
237 /* Bits in MMDREG_DEVS0. */
248 /* Bits in MMDREG_STAT2 */
297 EFAB_ERR("Not all MMDs came out of reset in time. MMDs "
298 "still in reset: %x\n", in_reset);
1315 * have all ones in either its high or low dwords. This approach is
1342 * Marked as static inline so that it will not be compiled in if not
1479 /* Copy data in */
2851 uint8_t in, cfg, out;
2856 /* Ensure XGXS and XAUI SerDes are held in reset */
2875 rc = i2c->read ( i2c, &i2c_max6647, RLHN, &in, EFAB_BYTE );
2879 if ( in != MAX_TEMP_THRESH ) {
2881 "confirmed=%d)\n", cfg, in );
2887 rc = i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
2934 rc = i2c->read ( i2c, &i2c_pca9539, P1_IN, &in, EFAB_BYTE );
2938 if ( in & ( 1 << P1_AFE_PWD_LBN ) )
2971 uint8_t in, cfg, out;
2988 (void) i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
3326 /* Patch in the board operations */
3342 /* Patch in MAC operations */
3348 /* Hook in the PHY ops */
3382 /* use card in internal SRAM mode */
3429 /* Set up TX and RX descriptor caches in SRAM */
4176 * and the board and phy variant. Hook in the op tables */
