Lines Matching refs:hw
130 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
134 gma_write16(hw, port, GM_SMI_DATA, val);
135 gma_write16(hw, port, GM_SMI_CTRL,
139 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
149 DBG(PFX "%s: phy write timeout\n", hw->dev[port]->name);
153 DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name);
157 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
161 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 *val = gma_read16(hw, port, GM_SMI_DATA);
177 DBG(PFX "%s: phy read timeout\n", hw->dev[port]->name);
180 DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name);
184 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187 __gm_phy_read(hw, port, reg, &v);
192 static void sky2_power_on(struct sky2_hw *hw)
195 sky2_write8(hw, B0_POWER_CTRL,
199 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
201 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
203 sky2_write8(hw, B2_Y2_CLK_GATE,
208 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
210 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
213 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
215 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
218 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
220 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
223 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
225 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
228 reg = sky2_read32(hw, B2_GP_IO);
230 sky2_write32(hw, B2_GP_IO, reg);
232 sky2_read32(hw, B2_GP_IO);
236 static void sky2_power_aux(struct sky2_hw *hw)
238 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
239 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
242 sky2_write8(hw, B2_Y2_CLK_GATE,
248 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
249 sky2_write8(hw, B0_POWER_CTRL,
254 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
259 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
261 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
262 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
263 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
264 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
266 reg = gma_read16(hw, port, GM_RX_CTRL);
268 gma_write16(hw, port, GM_RX_CTRL, reg);
296 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
298 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
302 !(hw->flags & SKY2_HW_NEWER_PHY)) {
303 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
310 if (hw->chip_id == CHIP_ID_YUKON_EC)
317 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
320 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
321 if (sky2_is_copper(hw)) {
322 if (!(hw->flags & SKY2_HW_GIGABIT)) {
326 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
327 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
331 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
333 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
344 && (hw->flags & SKY2_HW_NEWER_PHY)) {
357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
360 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
361 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
368 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
370 if (hw->pmd_type == 'P') {
372 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
375 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
377 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
389 if (sky2_is_copper(hw)) {
444 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
449 gma_write16(hw, port, GM_GP_CTRL, reg);
451 if (hw->flags & SKY2_HW_GIGABIT)
452 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
454 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
455 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
461 switch (hw->chip_id) {
466 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
472 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
477 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
489 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
493 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
496 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
506 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
515 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
521 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
524 hw, port, PHY_MARV_EXT_ADR, 3);
527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
534 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
548 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
553 gm_phy_write(hw, port, 0x18, 0xaa99);
554 gm_phy_write(hw, port, 0x17, 0x2011);
556 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
558 gm_phy_write(hw, port, 0x18, 0xa204);
559 gm_phy_write(hw, port, 0x17, 0x2002);
563 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
564 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
565 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
567 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
568 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
569 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
570 hw->chip_id < CHIP_ID_YUKON_SUPR) {
572 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
580 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
586 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
588 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
594 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
598 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
599 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
602 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
605 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
606 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
607 sky2_pci_read32(hw, PCI_DEV_REG1);
609 if (hw->chip_id == CHIP_ID_YUKON_FE)
610 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
611 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
612 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
615 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
621 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
624 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
626 if (hw->flags & SKY2_HW_NEWER_PHY) {
628 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
630 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
633 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
636 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
640 gma_write16(hw, port, GM_GP_CTRL,
643 if (hw->chip_id != CHIP_ID_YUKON_EC) {
644 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
646 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
648 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
651 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
658 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
661 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
662 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
664 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
665 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
668 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
670 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
671 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
672 hw->chip_id == CHIP_ID_YUKON_FE_P ||
673 hw->chip_id == CHIP_ID_YUKON_SUPR) {
675 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
678 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
682 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
687 const u8 *addr = hw->dev[port]->ll_addr;
689 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
690 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
692 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
694 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
697 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
699 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
700 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
701 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
702 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
703 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
706 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
709 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
711 sky2_phy_power_up(hw, port);
712 sky2_phy_init(hw, port);
715 reg = gma_read16(hw, port, GM_PHY_ADDR);
716 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
719 gma_read16(hw, port, i);
720 gma_write16(hw, port, GM_PHY_ADDR, reg);
723 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
726 gma_write16(hw, port, GM_RX_CTRL,
730 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
733 gma_write16(hw, port, GM_TX_PARAM,
743 gma_write16(hw, port, GM_SERIAL_MODE, reg);
746 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
749 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
752 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
753 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
754 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
757 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
759 if (hw->chip_id == CHIP_ID_YUKON_EX ||
760 hw->chip_id == CHIP_ID_YUKON_FE_P)
763 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
765 if (hw->chip_id == CHIP_ID_YUKON_XL) {
767 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
770 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
776 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
777 hw->chip_rev == CHIP_REV_YU_FE2_A0)
779 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
782 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
783 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
786 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
787 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
788 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
790 sky2_set_tx_stfwd(hw, port);
793 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
794 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
796 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
798 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
803 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
807 /* convert from K bytes to qwords used for hw register */
812 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
813 sky2_write32(hw, RB_ADDR(q, RB_START), start);
814 sky2_write32(hw, RB_ADDR(q, RB_END), end);
815 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
816 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
825 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
826 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
829 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
830 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
835 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
838 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
839 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
843 static void sky2_qset(struct sky2_hw *hw, u16 q)
845 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
848 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
854 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
857 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
858 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
859 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
860 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
861 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
862 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
864 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
894 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
898 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
950 sky2_write32(sky2->hw,
967 struct sky2_hw *hw = sky2->hw;
972 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
975 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
976 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
981 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
984 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1026 if (!(sky2->hw->flags & SKY2_HW_RAM_BUFFER)) {
1035 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1046 struct sky2_hw *hw = sky2->hw;
1052 sky2_qset(hw, rxq);
1055 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1056 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1060 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1061 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1062 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1063 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1065 sky2_prefetch_init(hw
1067 if (!(hw->flags & SKY2_HW_NEW_LE))
1086 sky2_rx_map_iob(hw->pdev, re, sky2->rx_data_size);
1097 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1099 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1100 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1131 struct sky2_hw *hw = sky2->hw;
1161 sky2_mac_init(hw, port);
1164 ramsize = sky2_read8(hw, B2_E_0) * 4;
1168 hw->flags |= SKY2_HW_RAM_BUFFER;
1175 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1176 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1179 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1183 sky2_qset(hw, txqaddr[port]);
1186 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1187 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1190 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1191 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1192 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1194 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1202 imask = sky2_read32(hw, B0_IMSK);
1204 sky2_write32(hw, B0_IMSK, imask);
1207 dev->name, hw->st_le, hw->st_dma, sky2->rx_le, sky2->rx_le_map,
1240 struct sky2_hw *hw = sky2->hw;
1269 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1314 struct sky2_hw *hw = sky2->hw;
1326 imask = sky2_read32(hw, B0_IMSK);
1328 sky2_write32(hw, B0_IMSK, imask);
1330 sky2_gmac_reset(hw, port);
1333 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1334 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1336 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1339 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1341 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1343 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1346 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1347 && port == 0 && hw->dev[1]))
1348 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1351 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1355 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1356 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1359 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1363 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1366 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1370 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1371 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1373 sky2_phy_power_down(hw, port);
1376 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1386 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1388 if (hw->flags & SKY2_HW_FIBRE_PHY)
1391 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1410 struct sky2_hw *hw = sky2->hw;
1421 reg = gma_read16(hw, port, GM_GP_CTRL);
1423 gma_write16(hw, port, GM_GP_CTRL, reg);
1425 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1430 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1441 struct sky2_hw *hw = sky2->hw;
1445 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1447 reg = gma_read16(hw, port, GM_GP_CTRL);
1449 gma_write16(hw, port, GM_GP_CTRL, reg);
1454 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1458 sky2_phy_init(hw, port);
1463 struct sky2_hw *hw = sky2->hw;
1467 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1468 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1479 sky2->speed = sky2_phy_speed(hw, aux);
1498 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1502 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1504 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1510 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1512 struct net_device *dev = hw->dev[port];
1516 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1517 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1529 sky2->speed = sky2_phy_speed(hw, phystat);
1559 sky2_rx_map_iob(sky2->hw->pdev, re, hdr_space);
1586 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
1587 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
1642 static void sky2_status_intr(struct sky2_hw *hw, u16 idx)
1649 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1661 dev = hw->dev[port];
1666 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1688 sky2_tx_done(hw->dev[0], status & 0xfff);
1689 if (hw->dev[1])
1690 sky2_tx_done(hw->dev[1],
1698 } while (hw->st_idx != idx);
1701 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1704 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
1707 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
1710 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1712 struct net_device *dev = hw->dev[port];
1714 DBGIO(PFX "%s: hw error interrupt status 0x%x\n", dev->name, status);
1719 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1724 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1729 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1734 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1739 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1743 static void sky2_hw_intr(struct sky2_hw *hw)
1745 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1746 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1751 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1756 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1757 pci_err = sky2_pci_read16(hw, PCI_STATUS);
1760 sky2_pci_write16(hw, PCI_STATUS,
1762 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1769 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1770 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
1771 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
1775 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
1776 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1780 sky2_hw_error(hw, 0, status);
1783 sky2_hw_error(hw, 1, status);
1786 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1788 struct net_device *dev = hw->dev[port];
1789 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1794 gma_read16(hw, port, GM_RX_IRQ_SRC);
1797 gma_read16(hw, port, GM_TX_IRQ_SRC);
1800 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1804 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1809 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
1812 struct net_device *dev = hw->dev[port];
1818 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
1821 (int) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_LAST_IDX)),
1822 (int) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)),
1825 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
1829 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
1834 sky2_hw_intr(hw);
1837 sky2_mac_intr(hw, 0);
1840 sky2_mac_intr(hw, 1);
1843 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
1846 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
1849 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
1852 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
1858 struct sky2_hw *hw = sky2->hw;
1859 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
1863 sky2_err_intr(hw, status);
1866 sky2_phy_intr(hw, 0);
1869 sky2_phy_intr(hw, 1);
1871 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
1872 sky2_status_intr(hw, idx);
1878 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
1879 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1880 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1882 sky2_read32(hw, B0_Y2_SP_LISR);
1886 static u32 sky2_mhz(const struct sky2_hw *hw)
1888 switch (hw->chip_id) {
1911 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1913 return sky2_mhz(hw) * us;
1916 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
1918 return clk / sky2_mhz(hw);
1921 static int sky2_init(struct sky2_hw *hw)
1926 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1928 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1930 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1931 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
1933 switch(hw->chip_id) {
1935 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
1939 hw->flags = SKY2_HW_GIGABIT
1945 hw->flags = SKY2_HW_GIGABIT
1953 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
1957 hw->flags = SKY2_HW_GIGABIT;
1964 hw->flags = SKY2_HW_NEWER_PHY
1971 hw->flags = SKY2_HW_GIGABIT
1979 hw->flags = SKY2_HW_GIGABIT
1984 DBG(PFX "unsupported chip type 0x%x\n", hw->chip_id);
1988 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
1989 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
1990 hw->flags |= SKY2_HW_FIBRE_PHY;
1992 hw->ports = 1;
1993 t8 = sky2_read8(hw, B2_Y2_HW_RES);
1995 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1996 ++hw->ports;
2002 static void sky2_reset(struct sky2_hw *hw)
2009 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2010 status = sky2_read16(hw, HCU_CCSR);
2013 sky2_write16(hw, HCU_CCSR, status);
2015 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2016 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2019 sky2_write8(hw, B0_CTST, CS_RST_SET);
2020 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2023 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2026 status = sky2_pci_read16(hw, PCI_STATUS);
2028 sky2_pci_write16(hw, PCI_STATUS, status);
2030 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2032 cap = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
2034 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2038 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2044 sky2_power_on(hw);
2045 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2047 for (i = 0; i < hw->ports; i++) {
2048 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2049 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2051 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2052 hw->chip_id == CHIP_ID_YUKON_SUPR)
2053 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2059 sky2_write32(hw, B2_I2C_IRQ, 1);
2062 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2063 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2065 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2068 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2071 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2072 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2075 for (i = 0; i < hw->ports; i++)
2076 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2079 for (i = 0; i < hw->ports; i++) {
2080 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2082 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2083 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2084 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2085 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2086 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2087 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2088 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2089 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2090 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2091 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2092 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2093 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2096 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2098 for (i = 0; i < hw->ports; i++)
2099 sky2_gmac_reset(hw, i);
2101 memset(hw->st_le, 0, STATUS_LE_BYTES);
2102 hw->st_idx = 0;
2104 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2105 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2107 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2108 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2111 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2113 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2114 sky2_write8(hw, STAT_FIFO_WM, 16);
2117 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2118 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2120 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2122 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2123 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2124 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2127 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2129 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2130 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2131 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2134 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2136 if (sky2_is_copper(hw)) {
2143 if (hw->flags & SKY2_HW_GIGABIT)
2157 struct sky2_hw *hw = sky2->hw;
2165 reg = gma_read16(hw, port, GM_RX_CTRL);
2170 gma_write16(hw, port, GM_MC_ADDR_H1,
2172 gma_write16(hw, port, GM_MC_ADDR_H2,
2174 gma_write16(hw, port, GM_MC_ADDR_H3,
2176 gma_write16(hw, port, GM_MC_ADDR_H4,
2179 gma_write16(hw, port, GM_RX_CTRL, reg);
2183 static struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2194 dev->dev = &hw->pdev->dev;
2198 sky2->hw = hw;
2206 sky2->advertising = sky2_supported_modes(hw);
2208 hw->dev[port] = dev;
2213 memcpy(dev->hw_addr, (void *)(hw->regs + B2_MAC_1 + port * 8), ETH_ALEN);
2249 struct sky2_hw *hw = sky2->hw;
2251 u32 imask = sky2_read32(hw, B0_IMSK);
2256 sky2_write32(hw, B0_IMSK, imask);
2271 struct sky2_hw *hw;
2278 hw = zalloc(sizeof(*hw));
2279 if (!hw) {
2284 hw->pdev = pdev;
2286 hw->regs = (unsigned long)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0), 0x4000);
2287 if (!hw->regs) {
2293 hw->st_le = malloc_dma(STATUS_LE_BYTES, STATUS_RING_ALIGN);
2294 if (!hw->st_le)
2296 hw->st_dma = virt_to_bus(hw->st_le);
2297 memset(hw->st_le, 0, STATUS_LE_BYTES);
2299 err = sky2_init(hw);
2305 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
2308 sky2_reset(hw);
2310 dev = sky2_init_netdev(hw, 0);
2324 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2328 if (hw->ports > 1) {
2331 dev1 = sky2_init_netdev(hw, 1);
2336 hw->dev[1] = NULL;
2351 sky2_write8(hw, B0_CTST, CS_RST_SET);
2352 free_dma(hw->st_le, STATUS_LE_BYTES);
2354 iounmap((void *)hw->regs);
2356 free(hw);
2364 struct sky2_hw *hw = pci_get_drvdata(pdev);
2367 if (!hw)
2370 for (i = hw->ports-1; i >= 0; --i)
2371 unregister_netdev(hw->dev[i]);
2373 sky2_write32(hw, B0_IMSK, 0);
2375 sky2_power_aux(hw);
2377 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2378 sky2_write8(hw, B0_CTST, CS_RST_SET);
2379 hw, B0_CTST);
2381 free_dma(hw->st_le, STATUS_LE_BYTES);
2383 for (i = hw->ports-1; i >= 0; --i) {
2384 netdev_nullify(hw->dev[i]);
2385 netdev_put(hw->dev[i]);
2388 iounmap((void *)hw->regs);
2389 free(hw);
