Lines Matching refs:Emit
140 selector->Emit(opcode, g.DefineAsRegister(node),
148 selector->Emit(opcode, g.DefineAsRegister(node),
157 selector->Emit(opcode, g.DefineAsRegister(node),
237 selector->Emit(opcode, arraysize(outputs), outputs, arraysize(inputs),
312 selector->Emit(opcode, output_count, outputs, input_count, inputs);
340 selector->Emit(opcode | AddressingModeField::encode(kMode_MRI),
345 selector->Emit(kMips64Dadd | AddressingModeField::encode(kMode_None),
347 // Emit desired load opcode, using temp addr_reg.
348 selector->Emit(opcode | AddressingModeField::encode(kMode_MRI),
435 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
471 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
476 Emit(kMips64Dadd | AddressingModeField::encode(kMode_None), addr_reg,
478 // Emit desired store opcode, using temp addr_reg.
479 Emit
515 Emit(kMips64Ext, g.DefineAsRegister(node),
530 Emit(kMips64Ins, g.DefineSameAsFirst(node),
566 Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(mleft.left().node()));
568 Emit(kMips64Dext, g.DefineAsRegister(node),
585 Emit(kMips64Dins, g.DefineSameAsFirst(node),
612 Emit(kMips64Nor32, g.DefineAsRegister(node),
621 Emit(kMips64Nor32, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
636 Emit(kMips64Nor, g.DefineAsRegister(node),
645 Emit(kMips64Nor, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
672 Emit(kMips64Shl, g.DefineAsRegister(node),
698 Emit(kMips64Ext, g.DefineAsRegister(node),
718 Emit(kMips64Seh, g.DefineAsRegister(node),
722 Emit(kMips64Seb, g.DefineAsRegister(node),
726 Emit(kMips64Shl, g.DefineAsRegister(node),
743 Emit(kMips64Dshl, g.DefineSameAsFirst(node),
765 Emit(kMips64Dshl, g.DefineAsRegister(node),
791 Emit(kMips64Dext, g.DefineAsRegister(node),
825 Emit(kMips64ByteSwap64, g.DefineAsRegister(node),
831 Emit(kMips64ByteSwap32, g.DefineAsRegister(node),
837 Emit(kMips64Ctz, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
843 Emit(kMips64Dctz, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
849 Emit(kMips64Popcnt, g.DefineAsRegister(node),
856 Emit(kMips64Dpopcnt, g.DefineAsRegister(node),
881 Emit(kMips64Lsa, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
893 Emit(kMips64Lsa, g.DefineAsRegister(node),
913 Emit(kMips64Dlsa, g.DefineAsRegister(node),
926 Emit(kMips64Dlsa, g.DefineAsRegister(node),
953 Emit(kMips64Shl | AddressingModeField::encode(kMode_None),
959 Emit(kMips64Lsa, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
966 Emit(kMips64Shl | AddressingModeField::encode(kMode_None), temp,
969 Emit(kMips64Sub | AddressingModeField::encode(kMode_None),
982 Emit(kMips64DMulHigh, g.DefineSameAsFirst(node),
1010 Emit(kMips64Dshl | AddressingModeField::encode(kMode_None),
1017 Emit(kMips64Dlsa, g.DefineAsRegister(node),
1024 Emit(kMips64Dshl | AddressingModeField::encode(kMode_None), temp,
1027 Emit(kMips64Dsub | AddressingModeField::encode(kMode_None),
1032 Emit(kMips64Dmul, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
1048 Emit(kMips64Ddiv, g.DefineSameAsFirst(node),
1055 Emit(kMips64Div, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()),
1063 Emit(kMips64DivU, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()),
1079 Emit(kMips64Dmod, g.DefineSameAsFirst(node),
1086 Emit(kMips64Mod, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
1094 Emit(kMips64ModU, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
1102 Emit(kMips64Ddiv, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()),
1110 Emit(kMips64DdivU, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()),
1118 Emit(kMips64Dmod, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
1126 Emit(kMips64DmodU, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
1174 Emit(kMips64FloorWD, g.DefineAsRegister(node),
1178 Emit(kMips64CeilWD, g.DefineAsRegister(node),
1182 Emit(kMips64RoundWD, g.DefineAsRegister(node),
1186 Emit(kMips64TruncWD, g.DefineAsRegister(node),
1198 Emit(kMips64FloorWS, g.DefineAsRegister(node),
1202 Emit(kMips64CeilWS, g.DefineAsRegister(node),
1206 Emit(kMips64RoundWS, g.DefineAsRegister(node),
1210 Emit(kMips64TruncWS, g.DefineAsRegister(node),
1214 Emit(kMips64TruncWS, g.DefineAsRegister(node),
1220 Emit(kMips64TruncWS, g.DefineAsRegister(node),
1250 this->Emit(kMips64TruncLS, output_count, outputs, 1, inputs);
1266 Emit(kMips64TruncLD, output_count, outputs, 1, inputs);
1282 Emit(kMips64TruncUlS, output_count, outputs, 1, inputs);
1299 Emit(kMips64TruncUlD, output_count, outputs, 1, inputs);
1327 Emit(kMips64Shl, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
1342 Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value));
1352 Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value));
1362 Emit(kMips64Dext, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
1379 Emit(kMips64Dsar, g.DefineSameAsFirst(node),
1391 Emit(kMips64Ext, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
1403 Emit(kMips64CvtSW, g.DefineAsRegister(node),
1450 Emit(kMips64Float64InsertLowWord32, g.DefineAsRegister(node),
1468 Emit(kMips64MaddS, g.DefineAsRegister(node),
1476 Emit(kMips64MaddS, g.DefineAsRegister(node),
1493 Emit(kMips64MaddD, g.DefineAsRegister(node),
1501 Emit(kMips64MaddD, g.DefineAsRegister(node),
1518 Emit(kMips64MsubS, g.DefineAsRegister(node),
1534 Emit(kMips64MsubD, g.DefineAsRegister(node),
1565 Emit(kMips64ModD, g.DefineAsFixed(node, f0),
1572 Emit(kMips64Float32Max, g.DefineAsRegister(node),
1578 Emit(kMips64Float64Max, g.DefineAsRegister(node),
1584 Emit(kMips64Float32Min, g.DefineAsRegister(node),
1590 Emit(kMips64Float64Min, g.DefineAsRegister(node),
1669 Emit(opcode, g.DefineAsFixed(node, f0), g.UseFixed(node->InputAt(0), f2),
1677 Emit(opcode, g.DefineAsFixed(node, f0), g.UseFixed(node->InputAt(0), f12))
1688 Emit(kArchPrepareCallCFunction |
1695 Emit(kMips64StoreToStackSlot, g.NoOutput(), g.UseRegister(input.node()),
1702 Emit(kMips64StackClaim, g.NoOutput(),
1708 Emit(kMips64StoreToStackSlot, g.NoOutput(), g.UseRegister(input.node()),
1761 Emit(opcode | AddressingModeField::encode(kMode_MRI),
1765 Emit(kMips64Dadd | AddressingModeField::encode(kMode_None), addr_reg,
1767 // Emit desired load opcode, using temp addr_reg.
1768 Emit(opcode | AddressingModeField::encode(kMode_MRI),
1814 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
1819 Emit(kMips64Dadd | AddressingModeField::encode(kMode_None), addr_reg,
1821 // Emit desired store opcode, using temp addr_reg.
1822 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
1878 Emit(opcode, g.DefineAsRegister(node), offset_operand,
1884 Emit(opcode | AddressingModeField::encode(kMode_MRI),
1942 Emit(opcode, g.NoOutput(), offset_operand, g.UseImmediate(length),
1948 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
1963 selector->Emit(opcode, g.NoOutput(), left, right,
1969 selector->Emit(opcode, g.DefineAsRegister(cont->result()), left, right);
1972 selector->Emit(opcode, g.NoOutput(), left, right,
2105 selector->Emit(kMips64Dshl, leftOp, g.UseRegister(node->InputAt(0)),
2107 selector->Emit(kMips64Dshl, rightOp, g.UseRegister(node->InputAt(1)),
2127 selector->Emit(testOpcode, optimizedResult, g.UseRegister(node->InputAt(0)),
2130 selector->Emit(kMips64Dshl, leftOp, g.UseRegister(node->InputAt(0)),
2132 selector->Emit(kMips64Dshl, rightOp, g.UseRegister(node->InputAt(1)),
2134 selector->Emit(testOpcode, fullResult, leftOp, rightOp);
2136 selector->Emit(
2179 selector->Emit(opcode, g.NoOutput(), value_operand, g.TempImmediate(0),
2186 selector->Emit(opcode, g.NoOutput(), value_operand, g.TempImmediate(0),
2189 selector->Emit(opcode, g.DefineAsRegister(cont->result()), value_operand,
2309 // Continuation could not be combined with a compare, emit compare against 0.
2352 // Emit either ArchTableSwitch or ArchLookupSwitch.
2364 Emit(kMips64Sub, index_operand, value_operand,
2553 Emit(kMips64Float64InsertLowWord32, g.DefineSameAsFirst(node),
2562 Emit(kMips64Float64InsertHighWord32, g.DefineSameAsFirst(node),
2587 Emit(opcode | AddressingModeField::encode(kMode_MRI),
2591 Emit(kMips64Dadd | AddressingModeField::encode(kMode_None), addr_reg,
2593 // Emit desired load opcode, using temp addr_reg.
2594 Emit(opcode | AddressingModeField::encode(kMode_MRI),
2622 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
2627 Emit(kMips64Dadd | AddressingModeField::encode(kMode_None), addr_reg,
2629 // Emit desired store opcode, using temp addr_reg.
2630 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
