Lines Matching defs:lui
182 // specially coded on MIPS means that it is a lui/ori instruction, and that is
614 return opcode == LUI;
747 // Use just lui and jic instructions. Insert lower part of the target address in
751 // in jic register with lui instruction.
1794 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);
1817 lui(at, hi);
1949 void Assembler::lui(Register rd, int32_t j) {
1951 GenInstrImmediate(LUI, zero_reg, rd, j);
1956 // This instruction uses same opcode as 'lui'. The difference in encoding is
1957 // 'lui' has zero reg. for rs field.
1960 GenInstrImmediate(LUI, rs, rt, j);
3170 lui(at, lui_offset);
3185 lui(at, (imm32 & kHiMask) >> kLuiShift);
3214 // Interpret 2 instructions generated by li: lui/ori
3236 // On Mips, a target address is stored in a lui/ori instruction pair, each
3239 // On r6, target address is stored in a lui/jic pair, and both instr have to be
3260 // Must use 2 instructions to insure patchable code => use lui and jic
3271 // Must use 2 instructions to insure patchable code => just use lui and ori.
3272 // lui rt, upper-16.
3274 *p = LUI | rt_code | ((itarget & kHiMask) >> kLuiShift);
