Lines Matching refs:ULL
318 #define AMD64G_CC_MASK_O (1ULL << AMD64G_CC_SHIFT_O)
319 #define AMD64G_CC_MASK_S (1ULL << AMD64G_CC_SHIFT_S)
320 #define AMD64G_CC_MASK_Z (1ULL << AMD64G_CC_SHIFT_Z)
321 #define AMD64G_CC_MASK_A (1ULL << AMD64G_CC_SHIFT_A)
322 #define AMD64G_CC_MASK_C (1ULL << AMD64G_CC_SHIFT_C)
323 #define AMD64G_CC_MASK_P (1ULL << AMD64G_CC_SHIFT_P)
330 #define AMD64G_CC_MASK_ID (1ULL << AMD64G_CC_SHIFT_ID)
331 #define AMD64G_CC_MASK_AC (1ULL << AMD64G_CC_SHIFT_AC)
332 #define AMD64G_CC_MASK_D (1ULL << AMD64G_CC_SHIFT_D)
340 #define AMD64G_FC_MASK_C3 (1ULL << AMD64G_FC_SHIFT_C3)
341 #define AMD64G_FC_MASK_C2 (1ULL << AMD64G_FC_SHIFT_C2)
342 #define AMD64G_FC_MASK_C1 (1ULL << AMD64G_FC_SHIFT_C1)
343 #define AMD64G_FC_MASK_C0 (1ULL << AMD64G_FC_SHIFT_C0)
