Lines Matching defs:rD
70 - pretty dodgy exception semantics for {LD,ST}Mxx and {LD,ST}RD.
2643 Also produce the t/e chars for the 2nd, 3rd, 4th insns, for
7890 void mk_neon_elem_load_to_one_lane( UInt rD, UInt inc, UInt index,
7896 putDRegI64(rD, triop(Iop_SetElem8x8, getDRegI64(rD), mkU8(index),
7900 putDRegI64(rD, triop(Iop_SetElem16x4, getDRegI64(rD), mkU8(index),
7904 putDRegI64(rD, triop(Iop_SetElem32x2, getDRegI64(rD), mkU8(index),
7913 putDRegI64(rD + i * inc,
7915 getDRegI64(rD + i * inc),
7923 putDRegI64(rD + i * inc,
7925 getDRegI64(rD + i * inc),
7933 putDRegI64(rD + i * inc,
7935 getDRegI64(rD + i * inc),
7951 void mk_neon_elem_store_from_one_lane( UInt rD, UInt inc, UInt index,
7958 binop(Iop_GetElem8x8, getDRegI64(rD), mkU8(index)));
7962 binop(Iop_GetElem16x4, getDRegI64(rD), mkU8(index)));
7966 binop(Iop_GetElem32x2, getDRegI64(rD), mkU8(index)));
7975 binop(Iop_GetElem8x8, getDRegI64(rD + i * inc),
7980 binop(Iop_GetElem16x4, getDRegI64(rD + i * inc),
7985 binop(Iop_GetElem32x2, getDRegI64(rD + i * inc),
8392 UInt rD = (INSN(22,22) << 4) | INSN(15,12);
8446 mk_neon_elem_load_to_one_lane(rD, inc, i, N, size, addr);
8448 mk_neon_elem_store_from_one_lane(rD, inc, i, N, size, addr);
8453 DIP("d%u[%u]", rD + j * inc, i);
8496 putDRegI64(rD + r, unop(Iop_Dup8x8,
8501 putDRegI64(rD + r, unop(Iop_Dup16x4,
8506 putDRegI64(rD + r, unop(Iop_Dup32x2,
8516 putDRegI64(rD + r + i * inc,
8524 putDRegI64(rD + r + i * inc,
8532 putDRegI64(rD + r + i * inc,
8549 DIP("d%u[]", rD + r + i * inc);
8592 if (rD + regs > 32) return False;
8599 if (regs == 1 && inc == 1 && rD + 1 >= 32) return False;
8600 if (regs == 1 && inc == 2 && rD + 2 >= 32) return False;
8601 if (regs == 2 && inc == 2 && rD + 3 >= 32) return False;
8604 if (inc == 1 && rD + 2 >= 32) return False;
8605 if (inc == 2 && rD + 4 >= 32) return False;
8608 rD + 3 >= 32) return False;
8609 if (inc == 2 && rD + 6 >= 32) return False;
8646 putDRegI64(rD+r, loadLE(Ity_I64, mkexpr(addr)), IRTemp_INVALID);
8648 storeLE(mkexpr(addr), getDRegI64(rD+r));
8688 putDRegI64(rD + 0 * regstep, mkexpr(du0), IRTemp_INVALID);
8689 putDRegI64(rD + 1 * regstep, mkexpr(du1), IRTemp_INVALID);
8691 assign(du0, getDRegI64(rD + 0 * regstep));
8692 assign(du1, getDRegI64(rD + 1 * regstep));
8723 putDRegI64(rD + 0 * regstep, mkexpr(du0), IRTemp_INVALID);
8724 putDRegI64(rD + 1 * regstep, mkexpr(du1), IRTemp_INVALID);
8725 putDRegI64(rD + 2 * regstep, mkexpr(du2), IRTemp_INVALID);
8726 putDRegI64(rD + 3 * regstep, mkexpr(du3), IRTemp_INVALID);
8728 assign(du0, getDRegI64(rD + 0 * regstep));
8729 assign(du1, getDRegI64(rD + 1 * regstep));
8730 assign(du2, getDRegI64(rD + 2 * regstep));
8731 assign(du3, getDRegI64(rD + 3 * regstep));
8765 putDRegI64(rD + 0 * inc, mkexpr(du0), IRTemp_INVALID);
8766 putDRegI64(rD + 1 * inc, mkexpr(du1), IRTemp_INVALID);
8767 putDRegI64(rD + 2 * inc, mkexpr(du2), IRTemp_INVALID);
8769 assign(du0, getDRegI64(rD + 0 * inc));
8770 assign(du1, getDRegI64(rD + 1 * inc));
8771 assign(du2, getDRegI64(rD + 2 * inc));
8805 putDRegI64(rD + 0 * inc, mkexpr(du0), IRTemp_INVALID);
8806 putDRegI64(rD + 1 * inc, mkexpr(du1), IRTemp_INVALID);
8807 putDRegI64(rD + 2 * inc, mkexpr(du2), IRTemp_INVALID);
8808 putDRegI64(rD + 3 * inc, mkexpr(du3), IRTemp_INVALID);
8810 assign(du0, getDRegI64(rD + 0 * inc));
8811 assign(du1, getDRegI64(rD + 1 * inc));
8812 assign(du2, getDRegI64(rD + 2 * inc));
8813 assign(du3, getDRegI64(rD + 3 * inc));
8848 DIP("d%u-d%u", rD, rD + regs * (N + 1) - 1);
8855 DIP("d%u", rD + r + i * inc);
9064 /* ------------ smulwb<y><c> <Rd>,<Rn>,<Rm> ------------- */
9065 /* ------------ smulwt<y><c> <Rd>,<Rn>,<Rm> ------------- */
9125 /* ------------ pkhbt<c> Rd, Rn, Rm {,LSL #imm} ------------- */
9126 /* ------------ pkhtb<c> Rd, Rn, Rm {,ASR #imm} ------------- */
9186 /* ---------- usat<c> <Rd>,#<imm5>,<Rn>{,<shift>} ----------- */
9244 /* ----------- ssat<c> <Rd>,#<imm5>,<Rn>{,<shift>} ----------- */
9302 /* ----------- ssat16<c> <Rd>,#<imm>,<Rn> ----------- */
9366 /* -------------- usat16<c> <Rd>,#<imm4>,<Rn> --------------- */
9427 /* -------------- uadd16<c> <Rd>,<Rn>,<Rm> -------------- */
9476 /* -------------- sadd16<c> <Rd>,<Rn>,<Rm> -------------- */
9526 /* ---------------- usub16<c> <Rd>,<Rn>,<Rm> ---------------- */
9576 /* -------------- ssub16<c> <Rd>,<Rn>,<Rm> -------------- */
9626 /* ----------------- uadd8<c> <Rd>,<Rn>,<Rm> ---------------- */
9675 /* ------------------- sadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9725 /* ------------------- usub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9775 /* ------------------- ssub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9825 /* ------------------ qadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9870 /* ------------------ qsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
9915 /* ------------------ uqadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9960 /* ------------------ uqsub8<c> <Rd>,<Rn>,<Rm> ------------------ */
10005 /* ----------------- uhadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
10050 /* ----------------- uhadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
10095 /* ----------------- shadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
10140 /* ------------------ qadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
10185 /* ------------------ qsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
10230 /* ------------------- qsax<c> <Rd>,<Rn>,<Rm> ------------------- */
10301 /* ------------------- qasx<c> <Rd>,<Rn>,<Rm> ------------------- */
10369 /* ------------------- sasx<c> <Rd>,<Rn>,<Rm> ------------------- */
10443 /* --------------- smuad, smuadx<c><Rd>,<Rn>,<Rm> --------------- */
10444 /* --------------- smsad, smsadx<c><Rd>,<Rn>,<Rm> --------------- */
10522 /* --------------- smlad{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
10523 /* --------------- smlsd{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
10613 /* ----- smlabb, smlabt, smlatb, smlatt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10683 /* ----- smlalbb, smlalbt, smlaltb, smlaltt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10758 /* ----- smlawb, smlawt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10829 /* ------------------- sel<c> <Rd>,<Rn>,<Rm> -------------------- */
10917 /* ----------------- uxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
10980 /* --------------- usad8 Rd,Rn,Rm ---------------- */
10981 /* --------------- usada8 Rd,Rn,Rm,Ra ---------------- */
10983 UInt rD = 99, rN = 99, rM = 99, rA = 99;
10990 rD = INSNT1(11,8);
10992 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && rA != 13)
10998 rD = INSNA(19,16);
11002 if (rD != 15 && rN != 15 && rM != 15 /* but rA can be 15 */)
11017 putIRegT( rD, res, condT );
11019 putIRegA( rD, res, condT, Ijk_Boring );
11023 nCC(conq), rD, rN, rM );
11026 nCC(conq), rD, rN, rM, rA );
11033 /* ------------------ qadd<c> <Rd>,<Rn>,<Rm> ------------------- */
11084 /* ------------------ qdadd<c> <Rd>,<Rm>,<Rn> ------------------- */
11143 /* ------------------ qsub<c> <Rd>,<Rn>,<Rm> ------------------- */
11194 /* ------------------ qdsub<c> <Rd>,<Rm>,<Rn> ------------------- */
11253 /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
11298 /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
11343 /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
11388 /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
11433 /* ------------------ uqadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
11478 /* ------------------- uqsax<c> <Rd>,<Rn>,<Rm> ------------------- */
11547 /* ------------------- uqasx<c> <Rd>,<Rn>,<Rm> ------------------- */
11615 /* ------------------- usax<c> <Rd>,<Rn>,<Rm> ------------------- */
11693 /* ------------------- uasx<c> <Rd>,<Rn>,<Rm> ------------------- */
11769 /* ------------------- ssax<c> <Rd>,<Rn>,<Rm> ------------------- */
11843 /* ----------------- shsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
11888 /* ----------------- sxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
11963 /* ----------------- shasx<c> <Rd>,<Rn>,<Rm> ------------------- */
12060 /* ----------------- uhasx<c> <Rd>,<Rn>,<Rm> ------------------- */
12157 /* ----------------- shsax<c> <Rd>,<Rn>,<Rm> ------------------- */
12254 /* ----------------- uhsax<c> <Rd>,<Rn>,<Rm> ------------------- */
12351 /* ----------------- shsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
12396 /* ----------------- smmls{r}<c> <Rd>,<Rn>,<Rm>,<Ra> ------------------- */
12398 UInt rD = 99, rN = 99, rM = 99, rA = 99;
12408 rD = INSNT1(11,8);
12411 if (!isBadRegT(rD)
12420 rD = INSNA(19,16);
12424 if (rD != 15 && rM != 15 && rN != 15)
12443 putIRegT( rD, res, condT );
12445 putIRegA(rD, res, condT, Ijk_Boring);
12447 round ? "r" : "", nCC(conq), rD, rN, rM, rA);
13258 A1: cond 0001 1100 n d 1110 1001 t STLEXB Rd, Rt, [Rn]
13259 A1: cond 0001 1110 n d 1110 1001 t STLEXH Rd, Rt, [Rn]
13260 A1: cond 0001 1000 n d 1110 1001 t STLEX Rd, Rt, [Rn]
13261 A1: cond 0001 1010 n d 1110 1001 t STLEXD Rd, Rt, Rt+1, [Rn]
13269 T1: 111 0100 01100 n t 1111 1100 d STLEXB Rd, Rt, [Rn]
13270 T1: 111 0100 01100 n t 1111 1101 d STLEXH Rd, Rt, [Rn]
13271 T1: 111 0100 01100 n t 1111 1110 d STLEX Rd, Rt, [Rn]
13272 T1: 111 0100 01100 n t t2 1111 d STLEXD Rd, Rt, Rt2, [Rn]
14572 UInt rD = INSN(15,12);
14575 if (rD == 15) {
14577 /* When rD is 15, we are copying the top 4 bits of FPSCR
14589 putIRegT(rD, e, condT);
14591 putIRegA(rD, e, condT, Ijk_Boring);
14592 DIP("fmrx%s r%u, fpscr\n", nCC(conq), rD);
14602 UInt rD = INSN(15,12);
14606 isT ? getIRegT(rD) : getIRegA(rD), condT);
14607 DIP("fmxr%s fpscr, r%u\n", nCC(conq), rD);
14614 // VMOV dM, rD, rN
14617 UInt rD = INSN(15,12); /* lo32 */
14619 if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))) {
14626 isT ? getIRegT(rD) : getIRegA(rD))),
14628 DIP("vmov%s d%u, r%u, r%u\n", nCC(conq), dM, rD, rN);
14634 // VMOV rD, rN, dM
14637 UInt rD = INSN(15,12); /* lo32 */
14639 if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))
14640 || rD == rN) {
14649 putIRegT(rD, lo32, condT);
14652 putIRegA(rD, lo32, condT, Ijk_Boring);
14654 DIP("vmov%s r%u, r%u, d%u\n", nCC(conq), rD, rN, dM);
14705 // VMOV rD[x], rT (ARM core register to scalar)
14707 UInt rD = (INSN(7,7) << 4) | INSN(19,16);
14716 putDRegI64(rD, triop(Iop_SetElem8x8,
14717 getDRegI64(rD),
14722 DIP("vmov%s.8 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
14727 putDRegI64(rD, triop(Iop_SetElem16x4,
14728 getDRegI64(rD),
14733 DIP("vmov%s.16 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
14738 putDRegI64(rD, triop(Iop_SetElem32x2,
14739 getDRegI64(rD),
14743 DIP("vmov%s.32 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
14752 // VMOV rT, rD[x]
14809 UInt rD = (INSN(15,12) << 1) | INSN(22,22);
14816 putFReg(rD, unop(Iop_ReinterpI32asF32, mkU32(imm)), condT);
14817 DIP("fconsts%s s%u #%u", nCC(conq), rD, imm8);
14825 UInt rD = INSN(15,12) | (INSN(22,22) << 4);
14832 putDReg(rD, unop(Iop_ReinterpI64asF64, mkU64(imm)), condT);
14833 DIP("fconstd%s d%u #%u", nCC(conq), rD, imm8);
14842 UInt rD = (INSN(7,7) << 4) | INSN(19,16);
14846 if (rT == 15 || (isT && rT == 13) || size == 3 || (Q && (rD & 1))) {
14851 rD >>= 1;
14854 putQReg(rD, unop(Iop_Dup32x4, e), condT);
14857 putQReg(rD, unop(Iop_Dup16x8, unop(Iop_32to16, e)),
14861 putQReg(rD, unop(Iop_Dup8x16, unop(Iop_32to8, e)),
14867 DIP("vdup.%d q%u, r%u\n", 32 / (1<<size), rD, rT);
14871 putDRegI64(rD, unop(Iop_Dup32x2, e), condT);
14874 putDRegI64(rD, unop(Iop_Dup16x4, unop(Iop_32to16, e)),
14878 putDRegI64(rD, unop(Iop_Dup8x8, unop(Iop_32to8, e)),
14884 DIP("vdup.%d d%u, r%u\n", 32 / (1<<size), rD, rT);
15365 UInt rD = INSN(15,12);
15369 if (rD == 15) {
15379 putIRegT(rD, res, condT);
15381 putIRegA(rD, res, condT, Ijk_Boring);
15382 DIP("fmrs%s r%u, s%u\n", nCC(conq), rD, fN);
15385 isT ? getIRegT(rD) : getIRegA(rD)),
15387 DIP("fmsr%s s%u, r%u\n", nCC(conq), fN, rD);
16240 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
16254 case BITS4(0,1,0,0): /* ADD: Rd = Rn + shifter_operand */
16256 case BITS4(0,0,1,0): /* SUB: Rd = Rn - shifter_operand */
16258 case BITS4(0,0,1,1): /* RSB: Rd = shifter_operand - Rn */
16260 case BITS4(0,0,0,0): /* AND: Rd = Rn & shifter_operand */
16262 case BITS4(1,1,0,0): /* OR: Rd = Rn | shifter_operand */
16264 case BITS4(0,0,0,1): /* EOR: Rd = Rn ^ shifter_operand */
16266 case BITS4(1,1,1,0): /* BIC: Rd = Rn & ~shifter_operand */
16311 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
16342 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
16347 case BITS4(1,1,0,1): /* MOV: Rd = shifter_operand */
16348 case BITS4(1,1,1,1): { /* MVN: Rd = not(shifter_operand) */
16375 putIRegA( rD, mkexpr(res), condT, jk );
16383 nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf );
16391 if (rD != 0)
16392 break; /* rD must be zero */
16417 if (rD != 0)
16418 break; /* rD must be zero */
16445 case BITS4(0,1,0,1): /* ADC: Rd = Rn + shifter_operand + oldC */
16447 case BITS4(0,1,1,0): /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
16449 case BITS4(0,1,1,1): /* RSC: Rd = shifter_operand - Rn - (oldC ^ 1) */
16490 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
16516 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
16529 A5-20 1 | 16 cond 0101 UB0L Rn Rd imm12
16530 A5-22 1 | 32 cond 0111 UBOL Rn Rd imm5 sh2 0 Rm
16531 A5-24 2 | 16 cond 0101 UB1L Rn Rd imm12
16532 A5-26 2 | 32 cond 0111 UB1L Rn Rd imm5 sh2 0 Rm
16533 A5-28 3 | 16 cond 0100 UB0L Rn Rd imm12
16534 A5-32 3 | 32 cond 0110 UB0L Rn Rd imm5 sh2 0 Rm
16574 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
16594 if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
16600 if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
16646 assign(rDt, getIRegA(rD));
16681 mkexpr(taT), llGetIReg(rD), condT );
16682 /* "rD == 15 ? condT : IRTemp_INVALID": simply
16691 putIRegA( rD, mkexpr(tD),
16692 rD == 15 ? condT : IRTemp_INVALID, jk );
16696 loadGuardedLE( tD, ILGop_8Uto32, mkexpr(taT), llGetIReg(rD), condT );
16697 /* No point in similar 3rd arg complexity here, since we
16699 putIRegA( rD, mkexpr(tD), IRTemp_INVALID, Ijk_Boring );
16707 vassert(rD != rN); /* since we just wrote rD */
16716 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
16720 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
16724 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
16736 writeback, and the same register is specified for Rd and Rn,
16756 A5-36 1 | 16 cond 0001 U10L Rn Rd im4h 1SH1 im4l
16757 A5-38 1 | 32 cond 0001 U00L Rn Rd 0000 1SH1 Rm
16758 A5-40 2 | 16 cond 0001 U11L Rn Rd im4h 1SH1 im4l
16759 A5-42 2 | 32 cond 0001 U01L Rn Rd 0000 1SH1 Rm
16760 A5-44 3 | 16 cond 0000 U10L Rn Rd im4h 1SH1 im4l
16761 A5-46 3 | 32 cond 0000 U00L Rn Rd 0000 1SH1 Rm
16802 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
16833 if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
16839 if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
16850 if (bL == 1 && rD == 15 && condT != IRTemp_INVALID) {
16884 /* ll previous value of rD, for dealing with conditional loads */
16886 assign(llOldRd, llGetIReg(rD));
16897 unop(Iop_32to16, getIRegA(rD)), condT );
16904 putIRegA( rD, mkexpr(newRd), IRTemp_INVALID, Ijk_Boring );
16911 putIRegA( rD, mkexpr(newRd), IRTemp_INVALID, Ijk_Boring );
16918 putIRegA( rD, mkexpr(newRd), IRTemp_INVALID, Ijk_Boring );
16929 vassert(rD != rN); /* since we just wrote rD */
16935 case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
16938 name, nCC(INSN_COND), rD, dis_buf);
16941 name, nCC(INSN_COND), rD, dis_buf);
16953 writeback, and the same register is specified for Rd and Rn,
17155 UInt rD = INSN(15,12);
17165 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
17166 DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
17176 UInt rD = INSN(19,16);
17179 if (rD == 15 || rM == 15 || rS == 15) {
17197 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
17206 bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
17217 UInt rD = INSN(19,16);
17220 if (rD == 15 || rM == 15 || rN == 15) {
17229 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
17230 DIP("sdiv r%u, r%u, r%u\n", rD, rN, rM);
17239 UInt rD = INSN(19,16);
17242 if (rD == 15 || rM == 15 || rN == 15) {
17251 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
17252 DIP("udiv r%u, r%u, r%u\n", rD, rN, rM);
17262 UInt rD = INSN(19,16);
17271 if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
17294 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
17304 nCC(INSN_COND), rD, rM, rS, rN);
17490 // MRS rD, cpsr
17492 UInt rD = INSN(15,12);
17493 if (rD != 15) {
17495 putIRegA( rD, mkexpr(apsr), condT, Ijk_Boring );
17496 DIP("mrs%s r%u, cpsr\n", nCC(INSN_COND), rD);
17527 UInt rD = INSN(15,12);
17535 if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
17565 putIRegA(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
17568 isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
17638 UInt rD = INSN(15,12);
17651 if (rD == 15 || rN == 15 || rT == 15
17652 || rD == rN || rD == rT)
17656 if (rD == 15 || (rT & 1) == 1 || rT == 14 || rN == 15
17657 || rD == rN || rD == rT || rD == rT+1)
17680 /* Set rD to 1 on failure, 0 on success. Currently we have
17686 putIRegA(rD, mkexpr(resSC32),
17690 nm, nCC(INSN_COND), rD, rT, rT+1, rN);
17693 nm, nCC(INSN_COND), rD, rT, rN);
17703 UInt rD = INSN(15,12);
17706 if (rD == 15) {
17710 putIRegA(rD,
17712 binop(Iop_And32, getIRegA(rD), mkU32(0xFFFF)),
17715 DIP("movt%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
17718 putIRegA(rD, mkU32(imm16), condT, Ijk_Boring);
17719 DIP("movw%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
17737 UInt rD = INSN(15,12);
17788 putIRegA(rD, mkexpr(dstT), condT, Ijk_Boring);
17789 DIP("%s%s r%u, r%u, ROR #%d\n", nm, nCC(INSN_COND), rD, rM, rot);
17798 UInt rD = INSN(15,12);
17802 if (rD == 15 || msb < lsb) {
17814 assign(olddst, getIRegA(rD));
17825 putIRegA(rD, mkexpr(newdst), condT, Ijk_Boring);
17829 nCC(INSN_COND), rD, lsb, msb-lsb+1);
17832 nCC(INSN_COND), rD, rN, lsb, msb-lsb+1);
17842 UInt rD = INSN(15,12);
17848 if (rD == 15 || rN == 15 || msb >= 32) {
17866 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
17870 nCC(INSN_COND), rD, rN, lsb, wm1 + 1);
17880 A5-36 1 | 16 cond 0001 U100 Rn Rd im4h 11S1 im4l
17881 A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm
17882 A5-40 2 | 16 cond 0001 U110 Rn Rd im4h 11S1 im4l
17883 A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm
17884 A5-44 3 | 16 cond 0000 U100 Rn Rd im4h 11S1 im4l
17885 A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm
17926 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
17932 /* Require rD to be an even numbered register */
17933 if ((rD & 1) != 0)
17951 if (bS == 0 && (rN == rD || rN == rD+1))
17958 if (bS == 0 && (rN == rD || rN == rD+1))
17968 vassert((rD & 1) == 0); /* from tests above */
17969 if (bS == 0 && rD+1 == 15 && condT != IRTemp_INVALID) {
18009 strd rD, [sp, #-8]
18010 strd rD, [sp, #-16]
18016 && rN == 13 && rN != rD && rN != rD+1
18030 getIRegA(rD+0), condT );
18032 getIRegA(rD+1), condT );
18037 assign(oldRd0, llGetIReg(rD+0));
18038 assign(oldRd1, llGetIReg(rD+1));
18044 putIRegA( rD+0, mkexpr(newRd0), IRTemp_INVALID, Ijk_Boring );
18048 putIRegA( rD+1, mkexpr(newRd1), IRTemp_INVALID, Ijk_Boring );
18058 vassert(rD+0 != rN); /* since we just wrote rD+0 */
18059 vassert(rD+1 != rN); /* since we just wrote rD+1 */
18067 case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
18070 name, nCC(INSN_COND), rD, dis_buf);
18073 name, nCC(INSN_COND), rD, dis_buf);
18088 UInt rD = INSN(15,12);
18092 if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
18105 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
18107 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
18118 UInt rD = INSN(15,12);
18122 if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
18135 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
18138 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
18149 UInt rD = INSN(15,12);
18150 if (rM != 15 && rD != 15) {
18154 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
18156 nCC(INSN_COND), rD, rM);
18164 UInt rD = INSN(15,12);
18165 if (rM != 15 && rD != 15) {
18186 putIRegA(rD, mkexpr(irt_res), condT, Ijk_Boring);
18187 DIP("revsh%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
18194 UInt rD = INSN(15,12);
18196 if (rD != 15 && rM != 15) {
18200 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
18201 DIP("rbit r%u, r%u\n", rD, rM);
18211 UInt rD = INSN(19,16);
18214 if (rD != 15 && rM != 15 && rN != 15) {
18220 putIRegA(rD, res, condT, Ijk_Boring);
18222 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM);
18232 UInt rD = INSN(19,16);
18236 if (rD != 15 && rM != 15 && rN != 15) {
18244 putIRegA(rD, res, condT, Ijk_Boring);
18246 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM, rA);
18694 UInt rD = INSN(15,12);
18695 if (rD <= 14) {
18697 putIRegA(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32),
18699 DIP("mrc%s p15,0, r%u, c13, c0, 3\n", nCC(INSN_COND), rD);
18714 UInt rD = INSN(15,12);
18715 if (rD <= 14) {
18717 putIRegA(rD, mkU32(0), condT, Ijk_Boring);
18718 DIP("mrc%s p15,0, r%u, c9, c14, 0\n", nCC(INSN_COND), rD);
19443 /* ---------------- NEGS Rd, Rm ---------------- */
19444 /* Rd = -Rm */
19446 UInt rD = INSN0(2,0);
19451 // rD can never be r15
19452 putIRegT(rD, binop(Iop_Sub32, mkexpr(zero), mkexpr(arg)), condT);
19454 DIP("negs r%u, r%u\n", rD, rM);
19459 /* ---------------- MVNS Rd, Rm ---------------- */
19460 /* Rd = ~Rm */
19462 UInt rD = INSN0(2,0);
19469 // rD can never be r15
19470 putIRegT(rD, mkexpr(res), condT);
19473 DIP("mvns r%u, r%u\n", rD, rM);
19478 /* ---------------- ORRS Rd, Rm ---------------- */
19481 /* ---------------- ANDS Rd, Rm ---------------- */
19484 /* ---------------- EORS Rd, Rm ---------------- */
19487 /* ---------------- MULS Rd, Rm ---------------- */
19490 /* Rd = Rd `op` Rm */
19492 UInt rD = INSN0(2,0);
19498 assign( res, binop(anOp, getIRegT(rD), getIRegT(rM) ));
19500 // rD can never be r15
19501 putIRegT(rD, mkexpr(res), condT);
19504 DIP("%s r%u, r%u\n", anOpNm, rD, rM);
19509 /* ---------------- BICS Rd, Rm ---------------- */
19510 /* Rd = Rd & ~Rm */
19512 UInt rD = INSN0(2,0);
19518 assign( res, binop(Iop_And32, getIRegT(rD),
19521 // rD can never be r15
19522 putIRegT(rD, mkexpr(res), condT);
19525 DIP("bics r%u, r%u\n", rD, rM);
19530 /* ---------------- ADCS Rd, Rm ---------------- */
19531 /* Rd = Rd + Rm + oldC */
19533 UInt rD = INSN0(2,0);
19538 assign(argL, getIRegT(rD));
19544 // rD can never be r15
19545 putIRegT(rD, mkexpr(res), condT);
19548 DIP("adcs r%u, r%u\n", rD, rM);
19553 /* ---------------- SBCS Rd, Rm ---------------- */
19554 /* Rd = Rd - Rm - (oldC ^ 1) */
19556 UInt rD = INSN0(2,0);
19561 assign(argL, getIRegT(rD));
19567 // rD can never be r15
19568 putIRegT(rD, mkexpr(res), condT);
19571 DIP("sbcs r%u, r%u\n", rD, rM);
19576 Rd, Rm ---------------- */
19577 /* Rd = 8Uto32(Rm) */
19579 UInt rD = INSN0(2,0);
19580 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFF)),
19582 DIP("uxtb r%u, r%u\n", rD, rM);
19587 /* ---------------- SXTB Rd, Rm ---------------- */
19588 /* Rd = 8Sto32(Rm) */
19590 UInt rD = INSN0(2,0);
19591 putIRegT(rD, binop(Iop_Sar32,
19595 DIP("sxtb r%u, r%u\n", rD, rM);
19600 /* ---------------- UXTH Rd, Rm ---------------- */
19601 /* Rd = 16Uto32(Rm) */
19603 UInt rD = INSN0(2,0);
19604 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFFFF)),
19606 DIP("uxth r%u, r%u\n", rD, rM);
19611 /* ---------------- SXTH Rd, Rm ---------------- */
19612 /* Rd = 16Sto32(Rm) */
19614 UInt rD = INSN0(2,0);
19615 putIRegT(rD, binop(Iop_Sar32,
19619 DIP("sxth r%u, r%u\n", rD, rM);
19627 /* ---------------- LSLS Rs, Rd ---------------- */
19628 /* ---------------- LSRS Rs, Rd ---------------- */
19629 /* ---------------- ASRS Rs, Rd ---------------- */
19630 /* ---------------- RORS Rs, Rd ---------------- */
19631 /* Rd = Rd `op` Rs, and set flags */
19633 UInt rD = INSN0(2,0);
19641 assign(rDt, getIRegT(rD));
19647 dis_buf, &res, &resC, rDt, rSt, rD, rS
19653 dis_buf, &res, &resC, rDt, rSt, rD, rS
19659 dis_buf, &res, &resC, rDt, rSt, rD, rS
19665 dis_buf, &res, &resC, rDt, rSt, rD, rS
19673 putIRegT(rD, mkexpr(res), condT);
19676 DIP("%ss r%u, r%u\n", wot, rS, rD);
19682 /* ---------------- REV Rd, Rm ---------------- */
19683 /* ---------------- REV16 Rd, Rm ---------------- */
19685 UInt rD = INSN0(2,0);
19690 putIRegT(rD, mkexpr(res), condT);
19691 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM);
19696 /* ---------------- REVSH Rd, Rn ---------------- */
19698 UInt rD = INSN0(2,0);
19719 putIRegT(rD, mkexpr(irt_res), condT);
19720 DIP("revsh r%u, r%u\n", rD, rM);
19838 /* ---------------- ADD(HI) Rd, Rm ---------------- */
19842 UInt rD = (h1 << 3) | INSN0(2,0);
19844 if (rD == 15 && rM == 15) {
19848 assign( res, binop(Iop_Add32, getIRegT(rD), getIRegT(rM) ));
19849 if (rD != 15) {
19850 putIRegT( rD, mkexpr(res), condT );
19863 DIP("add(hi) r%u, r%u\n", rD, rM);
19870 /* ---------------- CMP(HI) Rd, Rm ---------------- */
19889 /* ---------------- MOV(HI) Rd, Rm ---------------- */
19893 UInt rD = (h1 << 3) | INSN0(2,0);
19894 /* The old ARM ARM seems to disallow the case where both Rd and
19899 if (rD != 15) {
19900 putIRegT( rD, mkexpr(val), condT );
19913 DIP("mov r%u, r%u\n", rD, rM);
20128 /* ---------------- ADDS Rd, Rn, #uimm3 ---------------- */
20129 /* ---------------- SUBS Rd, Rn, #uimm3 ---------------- */
20132 UInt rD = INSN0(2,0);
20138 putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
20143 DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3);
20149 /* ---------------- ADDS Rd, Rn, Rm ---------------- */
20150 /* ---------------- SUBS Rd, Rn, Rm ---------------- */
20153 UInt rD = INSN0(2,0);
20159 putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
20164 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
20170 /* ------------- LDR Rd, [Rn, Rm] ------------- */
20171 /* ------------- STR Rd, [Rn, Rm] ------------- */
20172 /* LDR/STR Rd, [Rn + Rm] */
20173 UInt rD = INSN0(2,0);
20182 loadGuardedLE( tD, ILGop_Ident32, ea, llGetIReg(rD), condT );
20183 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20185 storeGuardedLE(ea, getIRegT(rD), condT);
20189 DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
20195 /* ------------- LDRH Rd, [Rn, Rm] ------------- */
20196 /* ------------- STRH Rd, [Rn, Rm] ------------- */
20197 /* LDRH/STRH Rd, [Rn + Rm] */
20198 UInt rD = INSN0(2,0);
20207 loadGuardedLE(tD, ILGop_16Uto32, ea, llGetIReg(rD), condT);
20208 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20210 storeGuardedLE( ea, unop(Iop_32to16, getIRegT(rD)), condT );
20214 DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
20219 /* ------------- LDRSH Rd, [Rn, Rm] ------------- */
20220 /* LDRSH Rd, [Rn + Rm] */
20221 UInt rD = INSN0(2,0);
20228 loadGuardedLE(tD, ILGop_16Sto32, ea, llGetIReg(rD), condT);
20229 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20232 DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM);
20237 /* ------------- LDRSB Rd, [Rn, Rm] ------------- */
20238 /* LDRSB Rd, [Rn + Rm] */
20239 UInt rD = INSN0(2,0);
20246 loadGuardedLE(tD, ILGop_8Sto32, ea, llGetIReg(rD), condT);
20247 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20250 DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM);
20256 /* ------------- LDRB Rd, [Rn, Rm] ------------- */
20257 /* ------------- STRB Rd, [Rn, Rm] ------------- */
20258 /* LDRB/STRB Rd, [Rn + Rm] */
20259 UInt rD = INSN0(2,0);
20268 loadGuardedLE(tD, ILGop_8Uto32, ea, llGetIReg(rD), condT);
20269 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20271 storeGuardedLE( ea, unop(Iop_32to8, getIRegT(rD)), condT );
20275 DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
20309 /* ---------------- ADD rD, PC, #imm8 * 4 ---------------- */
20311 /* rD = align4(PC) + imm8 * 4 */
20312 UInt rD = INSN0(10,8);
20314 putIRegT(rD, binop(Iop_Add32,
20318 DIP("add r%u, pc, #%u\n", rD, imm8 * 4);
20323 /* ---------------- ADD rD, SP, #imm8 * 4 ---------------- */
20324 UInt rD = INSN0(10,8);
20326 putIRegT(rD, binop(Iop_Add32, getIRegT(13), mkU32(imm8 * 4)),
20328 DIP("add r%u, r13, #%u\n", rD, imm8 * 4);
20348 UInt rD = INSN0(10,8);
20356 putIRegT(rD, mkexpr(res), condT);
20359 DIP("movs r%u, #%u\n", rD, uimm8);
20364 /* ------------- LDR Rd, [PC, #imm8 * 4] ------------- */
20365 /* LDR Rd, [align4(PC) + imm8 * 4] */
20366 UInt rD = INSN0(10,8);
20375 loadGuardedLE( tD, ILGop_Ident32, mkexpr(ea), llGetIReg(rD), condT );
20376 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20379 DIP("ldr r%u, [pc, #%u]\n", rD, imm8 * 4);
20385 /* ------------- LDR Rd, [Rn, #imm5 * 4] ------------- */
20386 /* ------------- STR Rd, [Rn, #imm5 * 4] ------------- */
20387 /* LDR/STR Rd, [Rn + imm5 * 4] */
20388 UInt rD = INSN0(2,0);
20397 loadGuardedLE( tD, ILGop_Ident32, ea, llGetIReg(rD), condT );
20398 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20400 storeGuardedLE( ea, getIRegT(rD), condT );
20404 DIP("%s r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 4);
20410 /* ------------- LDRH Rd, [Rn, #imm5 * 2] ------------- */
20411 /* ------------- STRH Rd, [Rn, #imm5 * 2] ------------- */
20412 /* LDRH/STRH Rd, [Rn + imm5 * 2] */
20413 UInt rD = INSN0(2,0);
20422 loadGuardedLE( tD, ILGop_16Uto32, ea, llGetIReg(rD), condT );
20423 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20425 storeGuardedLE( ea, unop(Iop_32to16, getIRegT(rD)), condT );
20429 DIP("%sh r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 2);
20435 /* ------------- LDRB Rd, [Rn, #imm5] ------------- */
20436 /* ------------- STRB Rd, [Rn, #imm5] ------------- */
20437 /* LDRB/STRB Rd, [Rn + imm5] */
20438 UInt rD = INSN0(2,0);
20447 loadGuardedLE( tD, ILGop_8Uto32, ea, llGetIReg(rD), condT );
20448 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20450 storeGuardedLE( ea, unop(Iop_32to8, getIRegT(rD)), condT );
20454 DIP("%sb r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5);
20460 /* ------------- LDR Rd, [SP, #imm8 * 4] ------------- */
20461 /* ------------- STR Rd, [SP, #imm8 * 4] ------------- */
20462 /* LDR/STR Rd, [SP + imm8 * 4] */
20463 UInt rD = INSN0(10,8);
20471 loadGuardedLE( tD, ILGop_Ident32, ea, llGetIReg(rD), condT );
20472 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
20474 storeGuardedLE(ea, getIRegT(rD), condT);
20478 DIP("%s r%u, [sp, #%u]\n", isLD ? "ldr" : "str", rD, imm8 * 4);
20577 /* ---------------- LSLS Rd, Rm, #imm5 ---------------- */
20578 /* ---------------- LSRS Rd, Rm, #imm5 ---------------- */
20579 /* ---------------- ASRS Rd, Rm, #imm5 ---------------- */
20580 UInt rD = INSN0(2,0);
20615 putIRegT(rD, mkexpr(res), condT);
20619 DIP("%ss r%u, r%u, #%u\n", wot, rD, rM, imm5);
20861 /* -------------- (T3) ADD{S}.W Rd, Rn, #constT -------------- */
20867 UInt rD = INSN1(11,8);
20868 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
20870 if (!valid && rD <= 14 && rN == 13)
20880 putIRegT(rD, mkexpr(res), condT);
20884 bS == 1 ? "s" : "", rD, rN, imm32);
20889 /* ---------------- (T4) ADDW Rd, Rn, #uimm12 -------------- */
20894 UInt rD = INSN1(11,8);
20895 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
20897 if (!valid && rD <= 14 && rN == 13)
20907 putIRegT(rD, mkexpr(res), condT);
20908 DIP("addw r%u, r%u, #%u\n", rD, rN, imm12);
20966 /* -------------- (T3) SUB{S}.W Rd, Rn, #constT -------------- */
20967 /* -------------- (T3) RSB{S}.W Rd, Rn, #constT -------------- */
20975 UInt rD = INSN1(11,8);
20976 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
20979 if (!valid && !isRSB && rN == 13 && rD != 15)
20991 putIRegT(rD, mkexpr(res), condT);
20999 isRSB ? "rsb" : "sub", bS == 1 ? "s" : "", rD, rN, imm32);
21004 /* -------------- (T4) SUBW Rd, Rn, #uimm12 ------------------- */
21009 UInt rD = INSN1(11,8);
21010 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
21012 if (!valid && rD == 13 && rN == 13)
21022 putIRegT(rD, mkexpr(res), condT);
21023 DIP("subw r%u, r%u, #%u\n", rD, rN, imm12);
21028 /* -------------- (T1) ADC{S}.W Rd, Rn, #constT -------------- */
21029 /* -------------- (T1) SBC{S}.W Rd, Rn, #constT -------------- */
21034 /* ADC: Rd = Rn + constT + oldC */
21035 /* SBC: Rd = Rn - constT - (oldC ^ 1) */
21038 UInt rD = INSN1(11,8);
21039 if (!isBadRegT(rN) && !isBadRegT(rD)) {
21056 putIRegT(rD, mkexpr(res), condT);
21067 putIRegT(rD, mkexpr(res), condT);
21076 nm, bS == 1 ? "s" : "", rD, rN, imm32);
21081 /* -------------- (T1) ORR{S}.W Rd, Rn, #constT -------------- */
21082 /* -------------- (T1) AND{S}.W Rd, Rn, #constT -------------- */
21083 /* -------------- (T1) BIC{S}.W Rd, Rn, #constT -------------- */
21084 /* -------------- (T1) EOR{S}.W Rd, Rn, #constT -------------- */
21094 UInt rD = INSN1(11,8);
21095 if (!isBadRegT(rN) && !isBadRegT(rD)) {
21117 putIRegT(rD, mkexpr(res), condT);
21129 nm, bS == 1 ? "s" : "", rD, rN, imm32);
21134 /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */
21135 /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */
21136 /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */
21143 UInt rD = INSN1(11,8);
21149 Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
21153 && rD != 15 && rN == 13 && imm5 <= 31 && how == 0) {
21159 && rD != 15 && rN == 13 && imm5 <= 5 && how == 0) {
21190 putIRegT(rD, mkexpr(res), condT);
21208 nm, bS ? "s" : "", rD, rN, dis_buf);
21213 /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
21214 /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */
21219 /* ADC: Rd = Rn + shifter_operand + oldC */
21220 /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
21222 UInt rD = INSN1(11,8);
21224 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
21252 putIRegT(rD, mkexpr(res), condT);
21263 putIRegT(rD, mkexpr(res), condT);
21273 nm, bS ? "s" : "", rD, rN, dis_buf);
21278 /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
21279 /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
21280 /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
21281 /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */
21282 /* ---------- (T1) ORN{S}.W Rd, Rn, Rm, {shift} ---------- */
21291 UInt rD = INSN1(11,8);
21293 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
21333 putIRegT(rD, mkexpr(res), condT);
21342 nm, bS ? "s" : "", rD, rN, dis_buf);
21347 /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */
21348 /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */
21349 /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */
21350 /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */
21356 UInt rD = INSN1(11,8);
21359 Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
21376 rD, mkexpr(res), condT);
21382 nm, bS ? "s" : "", rD, rN, rM);
21387 /* ------------ (T?) MOV{S}.W Rd, Rn, {shift} ------------ */
21388 /* ------------ (T?) MVN{S}.W Rd, Rn, {shift} ------------ */
21391 UInt rD = INSN1(11,8);
21396 ? (!isBadRegT(rD) && !isBadRegT(rN))
21397 : (rD != 15 && rN != 15 && (rD != 13 || rN != 13));
21415 putIRegT(rD, mkexpr(res), condT);
21422 isMVN ? "mvn" : "mov", bS ? "s" : "", rD, dis_buf);
21501 /* -------------- (T2) MOV{S}.W Rd, #constT -------------- */
21502 /* -------------- (T2) MVN{S}.W Rd, #constT -------------- */
21508 UInt rD = INSN1(11,8);
21509 if (!isBadRegT(rD)) {
21516 putIRegT(rD, mkexpr(res), condT);
21528 isMVN ? "mvn" : "mov", bS ? "s" : "", rD, imm32);
21533 /* -------------- (T3) MOVW Rd, #imm16 -------------- */
21537 UInt rD = INSN1(11,8);
21538 if (!isBadRegT(rD)) {
21541 putIRegT(rD, mkU32(imm16), condT);
21542 DIP("movw r%u, #%u\n", rD, imm16);
21547 /* ---------------- MOVT Rd, #imm16 ---------------- */
21551 UInt rD = INSN1(11,8);
21552 if (!isBadRegT(rD)) {
21558 binop(Iop_And32, getIRegT(rD), mkU32(0xFFFF)),
21560 putIRegT(rD, mkexpr(res), condT);
21561 DIP("movt r%u, #%u\n", rD, imm16);
22102 strd rD, [sp, #-8]
22103 strd rD, [sp, #-16]
22303 UInt rD = INSN1(11,8);
22307 if (!isBadRegT(rD) && !isBadRegT(rN) && msb <= 31) {
22324 putIRegT(rD, mkexpr(res), condT);
22327 isU ? "ubfx" : "sbfx", rD, rN, lsb, wm1 + 1);
22348 UInt rD = INSN1(11,8);
22351 if (!isBadRegT(rD) && !isBadRegT(rM)) {
22407 putIRegT(rD, mkexpr(dstT), condT);
22408 DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot);
22413 /* -------------- MUL.W Rd, Rn, Rm -------------- */
22417 UInt rD = INSN1(11,8);
22419 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
22422 putIRegT(rD, mkexpr(res), condT);
22423 DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM);
22428 /* -------------- SDIV.W Rd, Rn, Rm -------------- */
22432 UInt rD = INSN1(11,8);
22434 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
22441 putIRegT(rD, mkexpr(res), condT);
22442 DIP("sdiv.w r%u, r%u, r%u\n", rD, rN, rM);
22447 /* -------------- UDIV.W Rd, Rn, Rm -------------- */
22451 UInt rD = INSN1(11,8);
22453 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
22460 putIRegT(rD, mkexpr(res), condT);
22461 DIP("udiv.w r%u, r%u, r%u\n", rD, rN, rM);
22493 UInt rD = INSN1(11,8);
22495 if (!isBadRegT(rD) && !isBadRegT(rN)
22503 putIRegT(rD, mkexpr(res), condT);
22505 isMLA ? "mla" : "mls", rD, rN, rM, rA);
22513 /* rD = align4(PC) + imm32 */
22514 UInt rD = INSN1(11,8);
22515 if (!isBadRegT(rD)) {
22518 putIRegT(rD, binop(Iop_Add32,
22522 DIP("add r%u, pc, #%u\n", rD, imm32);
22602 UInt rD = INSN1(11,8);
22605 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
22611 putIRegT(rD, res, condT);
22613 bitR ? "r" : "", rD, rN, rM);
22624 UInt rD = INSN1(11,8);
22627 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && (rA != 13)) {
22635 putIRegT(rD, res, condT);
22637 bitR ? "r" : "", rD, rN, rM, rA);
22645 /* rD = align4(PC) - imm32 */
22646 UInt rD = INSN1(11,8);
22647 if (!isBadRegT(rD)) {
22650 putIRegT(rD, binop(Iop_Sub32,
22654 DIP("sub r%u, pc, #%u\n", rD, imm32);
22662 UInt rD = INSN1(11,8);
22666 if (isBadRegT(rD) || rN == 13 || msb < lsb) {
22678 assign(olddst, getIRegT(rD));
22689 putIRegT(rD, mkexpr(newdst), condT);
22693 rD, lsb, msb-lsb+1);
22696 rD, rN, lsb, msb-lsb+1);
22710 UInt rD = INSN1(11,8);
22713 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
22724 putIRegT(rD, mkexpr(res), condT);
22726 isU ? 'u' : 's', rD, rN, rM, rot);
22739 UInt rD = INSN1(11,8);
22742 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
22753 putIRegT(rD, mkexpr(res), condT);
22755 isU ? 'u' : 's', rD, rN, rM, rot);
22765 UInt rD = INSN1(11,8);
22767 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
22776 putIRegT(rD, mkexpr(res), condT);
22777 DIP("clz r%u, r%u\n", rD, rM1);
22787 UInt rD = INSN1(11,8);
22789 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
22793 putIRegT(rD, mkexpr(res), condT);
22794 DIP("rbit r%u, r%u\n", rD, rM1);
22806 UInt rD = INSN1(11,8);
22809 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
22813 putIRegT(rD, mkexpr(res), condT);
22814 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM1);
22825 UInt rD = INSN1(11,8);
22826 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
22847 putIRegT(rD, mkexpr(irt_res), condT);
22848 DIP("revsh r%u, r%u\n", rD, rM1);
22872 UInt rD = INSN1(11,8);
22873 if (!isBadRegT(rD)) {
22875 putIRegT( rD, mkexpr(apsr), condT );
22876 DIP("mrs r%u, cpsr\n", rD);
22949 UInt rD = INSN1(11,8);
22951 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
22952 && rD != rN && rD != rT) {
22963 /* Set rD to 1 on failure, 0 on success. Currently we have
22968 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
22969 DIP("strex r%u, r%u, [r%u, #+%u]\n", rD, rT, rN, imm8 * 4);
22979 UInt rD = INSN1(3,0);
22981 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
22982 && rD != rN && rD != rT) {
22992 /* Set rD to 1 on failure, 0 on success. Currently we have
22997 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
22998 DIP("strex%c r%u, r%u, [r%u]\n", isH ? 'h' : 'b', rD, rT, rN);
23008 UInt rD = INSN1(3,0);
23009 if (!isBadRegT(rD) && !isBadRegT(rT) && !isBadRegT(rT2)
23010 && rN != 15 && rD != rN && rD != rT && rD != rT2) {
23022 /* Set rD to 1 on failure, 0 on success. Currently we have
23027 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
23028 DIP("strexd r%u, r%u, r%u, [r%u]\n", rD, rT, rT2, rN);
23115 UInt rD = INSN1(15,12);
23116 if (!isBadRegT(rD)) {
23117 putIRegT(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32), condT);
23118 DIP("mrc p15,0, r%u, c13, c0, 3\n", rD);
23130 UInt rD = INSN1(15,12);
23131 if (!isBadRegT(rD)) {
23132 putIRegT(rD, mkU32(0), condT);
23133 DIP("mrc p15,0, r%u, c9, c14, 0\n", rD);
