Lines Matching refs:ov
2209 /* Interface to write XER[OV] */
2210 IRExpr* ov;
2212 ov = binop(Iop_And8, e, mkU8(1));
2213 stmt( IRStmt_Put( OFFB_XER_OV, ov ) );
2219 IRExpr* ov;
2221 ov = binop(Iop_And8, e, mkU8(1));
2226 stmt( IRStmt_Put( OFFB_XER_OV32, ov ) );
2281 /* get XER[OV], 32-bit interface */
2317 /* RES is the result of doing OP on ARGL and ARGR. Set %XER.OV and
2375 /* OV true if result can't be represented in 32 bits
2420 * then OV <- 1. If dest reg is 0 AND both dividend and divisor are non-zero,
2515 /* OV true if result can't be represented in 64 bits
2548 /* If argR == 0, we must set the OV bit. But there's another condition
2561 /* If argR == 0 or if argL >= argR, set OV. */
2568 /* OV true if result can't be represented in 64 bits
2619 /* Update the OV32 to match OV */
5469 /* OV is set to 1 if product isn't representable.
5471 * i.e. copy OV to OV32 and SO.
5511 * the LT, GT, and EQ bits of CR Field 0. In these cases, if OE=1 then OV is set
5547 * Field 0. In these cases, if OE=1 then OV is set to 1.
5583 * Field 0. In these cases, if OE=1 then OV is set to 1.
5598 // Same CR and OV rules as given for divweu above
