Lines Matching refs:rex
2144 (lowest bit of rex distinguishes R12/RSP)
2148 (lowest bit of rex distinguishes R12/RSP)
2276 /* Clear the W bit on a REX byte, thereby changing the operand size
2278 static inline UChar clearWBit ( UChar rex )
2280 return rex & ~(1<<3);
2284 /* Make up a REX byte, with W=1 (size=64), for a (greg,amode) pair. */
2317 /* Make up a REX byte, with W=1 (size=64), for a (greg,ereg) pair. */
2458 UChar rex;
2760 rex = clearWBit( rexAMode_R_enc_reg( 0, i->Ain.Alu32R.dst ) );
2761 if (rex != 0x40) *p++ = rex;
2766 rex = clearWBit( rexAMode_R_enc_reg( 0, i->Ain.Alu32R.dst) );
2767 if (rex != 0x40) *p++ = rex;
2774 rex = clearWBit(
2777 if (rex != 0x40) *p++ = rex;
2783 rex = clearWBit(
2786 if (rex != 0x40) *p++ = rex;
3217 rex = rexAMode_M(i->Ain.CLoad.dst, i->Ain.CLoad.addr);
3218 *p++ = i->Ain.CLoad.szB == 4 ? clearWBit(rex) : rex;
3246 rex = rexAMode_M(i->Ain.CStore.src, i->Ain.CStore.addr);
3247 *p++ = i->Ain.CStore.szB == 4 ? clearWBit(rex) : rex;
3262 /* Need REX.W = 1 here, but rexAMode_R does that for us. */
3323 /* note, 8-bit register rex trickyness. Be careful here. */
3355 rex = rexAMode_M( hregAMD64_RBX(), i->Ain.ACAS.addr );
3357 rex = clearWBit(rex);
3359 *p++ = rex; /* this can emit 0x40, which is pointless. oh well. */
3371 rex = rexAMode_M_enc(1, i->Ain.ACAS.addr );
3373 rex = clearWBit(rex);
3374 *p++ = rex;
3458 ensuring that REX.W = 0. */
3473 a rex byte of 0x40, since the mere presence of rex changes
3514 rex = rexAMode_R_enc_reg( vregEnc3210(i->Ain.SseSI2SF.dst),
3517 *p++ = toUChar(i->Ain.SseSI2SF.szS==4 ? clearWBit(rex) : rex);
3526 rex = rexAMode_R_reg_enc( i->Ain.SseSF2SI.dst,
3529 *p++ = toUChar(i->Ain.SseSF2SI.szD==4 ? clearWBit(rex) : rex);
3748 rex = clearWBit(
3753 case Asse_MOV: /*movups*/ XX(rex); XX(0x0F); XX(0x10); break;
3754 case Asse_OR: XX(rex); XX(0x0F); XX(0x56); break;
3755 case Asse_XOR: XX(rex); XX(0x0F); XX(0x57); break;
3756 case Asse_AND: XX(rex); XX(0x0F); XX(0x54); break;
3757 case Asse_ANDN: XX(rex); XX(0x0F); XX(0x55); break;
3758 case Asse_PACKSSD: XX(0x66); XX(rex); XX(0x0F); XX(0x6B); break;
3759 case Asse_PACKSSW: XX(0x66); XX(rex); XX(0x0F); XX(0x63); break;
3760 case Asse_PACKUSW: XX(0x66); XX(rex); XX(0x0F); XX(0x67); break;
3761 case Asse_ADD8: XX(0x66); XX(rex); XX(0x0F); XX(0xFC); break;
3762 case Asse_ADD16: XX(0x66); XX(rex); XX(0x0F); XX(0xFD); break;
3763 case Asse_ADD32: XX(0x66); XX(rex); XX(0x0F); XX(0xFE); break;
3764 case Asse_ADD64: XX(0x66); XX(rex); XX(0x0F); XX(0xD4); break;
3765 case Asse_QADD8S: XX(0x66); XX(rex); XX(0x0F); XX(0xEC); break;
3766 case Asse_QADD16S: XX(0x66); XX(rex); XX(0x0F); XX(0xED); break;
3767 case Asse_QADD8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDC); break;
3768 case Asse_QADD16U: XX(0x66); XX(rex); XX(0x0F); XX(0xDD); break;
3769 case Asse_AVG8U: XX(0x66); XX(rex); XX(0x0F); XX(0xE0); break;
3770 case Asse_AVG16U: XX(0x66); XX(rex); XX(0x0F); XX(0xE3); break;
3771 case Asse_CMPEQ8: XX(0x66); XX(rex); XX(0x0F); XX(0x74); break;
3772 case Asse_CMPEQ16: XX(0x66); XX(rex); XX(0x0F); XX(0x75); break;
3773 case Asse_CMPEQ32: XX(0x66); XX(rex); XX(0x0F); XX(0x76); break;
3774 case Asse_CMPGT8S: XX(0x66); XX(rex); XX(0x0F); XX(0x64); break;
3775 case Asse_CMPGT16S: XX(0x66); XX(rex); XX(0x0F); XX(0x65); break;
3776 case Asse_CMPGT32S: XX(0x66); XX(rex); XX(0x0F); XX(0x66); break;
3777 case Asse_MAX16S: XX(0x66); XX(rex); XX(0x0F); XX(0xEE); break;
3778 case Asse_MAX8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDE); break;
3779 case Asse_MIN16S: XX(0x66); XX(rex); XX(0x0F); XX(0xEA); break;
3780 case Asse_MIN8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDA); break;
3781 case Asse_MULHI16U: XX(0x66); XX(rex); XX(0x0F); XX(0xE4); break;
3782 case Asse_MULHI16S: XX(0x66); XX(rex); XX(0x0F); XX(0xE5); break;
3783 case Asse_MUL16: XX(0x66); XX(rex); XX(0x0F); XX(0xD5); break;
3784 case Asse_SHL16: XX(0x66); XX(rex); XX(0x0F); XX(0xF1); break;
3785 case Asse_SHL32: XX(0x66); XX(rex); XX(0x0F); XX(0xF2); break;
3786 case Asse_SHL64: XX(0x66); XX(rex); XX(0x0F); XX(0xF3); break;
3787 case Asse_SAR16: XX(0x66); XX(rex); XX(0x0F); XX(0xE1); break;
3788 case Asse_SAR32: XX(0x66); XX(rex); XX(0x0F); XX(0xE2); break;
3789 case Asse_SHR16: XX(0x66); XX(rex); XX(0x0F); XX(0xD1); break;
3790 case Asse_SHR32: XX(0x66); XX(rex); XX(0x0F); XX(0xD2); break;
3791 case Asse_SHR64: XX(0x66); XX(rex); XX(0x0F); XX(0xD3); break;
3792 case Asse_SUB8: XX(0x66); XX(rex); XX(0x0F); XX(0xF8); break;
3793 case Asse_SUB16: XX(0x66); XX(rex); XX(0x0F); XX(0xF9); break;
3794 case Asse_SUB32: XX(0x66); XX(rex); XX(0x0F); XX(0xFA); break;
3795 case Asse_SUB64: XX(0x66); XX(rex); XX(0x0F); XX(0xFB); break;
3796 case Asse_QSUB8S: XX(0x66); XX(rex); XX(0x0F); XX(0xE8); break;
3797 case Asse_QSUB16S: XX(0x66); XX(rex); XX(0x0F); XX(0xE9); break;
3798 case Asse_QSUB8U: XX(0x66); XX(rex); XX(0x0F); XX(0xD8); break;
3799 case Asse_QSUB16U: XX(0x66); XX(rex); XX(0x0F); XX(0xD9); break;
3800 case Asse_UNPCKHB: XX(0x66); XX(rex); XX(0x0F); XX(0x68); break;
3801 case Asse_UNPCKHW: XX(0x66); XX(rex); XX(0x0F); XX(0x69); break;
3802 case Asse_UNPCKHD: XX(0x66); XX(rex); XX(0x0F); XX(0x6A); break;
3803 case Asse_UNPCKHQ: XX(0x66); XX(rex); XX(0x0F); XX(0x6D); break;
3804 case Asse_UNPCKLB: XX(0x66); XX(rex); XX(0x0F); XX(0x60); break;
3805 case Asse_UNPCKLW: XX(0x66); XX(rex); XX(0x0F); XX(0x61); break;
3806 case Asse_UNPCKLD: XX(0x66); XX(rex); XX(0x0F); XX(0x62); break;
3807 case Asse_UNPCKLQ: XX(0x66); XX(rex); XX(0x0F); XX(0x6C); break;
3871 /* Need to compute the REX byte for the decl in order to prove
3877 rex = clearWBit(rexAMode_M_enc(1, i->Ain.EvCheck.amCounter));
3878 if (rex != 0x40) goto bad; /* We don't expect to need the REX byte. */
3887 /* Once again, verify we don't need REX. The encoding is FF /4.
3888 We don't need REX.W since by default FF /4 in 64-bit mode
3890 rex = clearWBit(rexAMode_M_enc(4, i->Ain.EvCheck.amFailAddr));
3891 if (rex != 0x40) goto bad;
