Lines Matching defs:rD
1137 Bool isLoad, HReg rD, ARMAMode1* amode ) {
1142 i->ARMin.LdSt32.rD = rD;
1149 HReg rD, ARMAMode2* amode ) {
1155 i->ARMin.LdSt16.rD = rD;
1161 Bool isLoad, HReg rD, ARMAMode1* amode ) {
1166 i->ARMin.LdSt8U.rD = rD;
1171 ARMInstr* ARMInstr_Ld8S ( ARMCondCode cc, HReg rD, ARMAMode2* amode ) {
1175 i->ARMin.Ld8S.rD = rD;
1534 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) {
1541 i->ARMin.Alu.dst = rD;
1546 i->ARMin.Add32.rD = rD;
1615 ppHRegARM(i->ARMin.LdSt32.rD);
1623 ppHRegARM(i->ARMin.LdSt32.rD);
1633 ppHRegARM(i->ARMin.LdSt16.rD);
1642 ppHRegARM(i->ARMin.LdSt16.rD);
1649 ppHRegARM(i->ARMin.LdSt8U.rD);
1657 ppHRegARM(i->ARMin.LdSt8U.rD);
1665 ppHRegARM(i->ARMin.Ld8S.rD);
2044 ppHRegARM(i->ARMin.Add32.rD);
2112 addHRegUse(u, HRmWrite, i->ARMin.LdSt32.rD);
2114 addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD);
2116 addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD);
2122 addHRegUse(u, HRmWrite, i->ARMin.LdSt16.rD);
2124 addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD);
2126 addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD);
2132 addHRegUse(u, HRmWrite, i->ARMin.LdSt8U.rD);
2134 addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD);
2136 addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD);
2141 addHRegUse(u, HRmWrite, i->ARMin.Ld8S.rD);
2143 addHRegUse(u, HRmRead, i->ARMin.Ld8S.rD);
2383 addHRegUse(u, HRmWrite, i->ARMin.Add32.rD);
2435 i->ARMin.LdSt32.rD = lookupHRegRemap(m, i->ARMin.LdSt32.rD);
2439 i->ARMin.LdSt16.rD = lookupHRegRemap(m, i->ARMin.LdSt16.rD);
2443 i->ARMin.LdSt8U.rD = lookupHRegRemap(m, i->ARMin.LdSt8U.rD);
2447 i->ARMin.Ld8S.rD = lookupHRegRemap(m, i->ARMin.Ld8S.rD);
2598 i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD);
2913 static UInt* imm32_to_ireg ( UInt* p, Int rD, UInt imm32 )
2916 vassert(rD >= 0 && rD <= 14); // r15 not good to mess with!
2920 instr = XXXXXX__(X1110,X0011,X1010,X0000,rD,X0000);
2925 // ldr rD, [pc]
2926 instr = XXXXX___(X1110,X0101,X1001,X1111,rD);
2936 /* Generate movw rD, #low16. Then, if the high 16 are
2937 nonzero, generate movt rD, #high16. */
2940 instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
2945 instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
2957 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2960 rN = rD;
2965 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2968 rN = rD;
2973 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2976 rN = rD;
2981 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2984 rN = rD;
2995 static UInt* imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
2998 /* Generate movw rD, #low16 ; movt rD, #high16. */
3002 instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
3006 instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
3018 static Bool is_imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
3021 /* Generate movw rD, #low16 ; movt rD, #high16. */
3025 i0 = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
3028 i1 = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
3039 Bool isLoad, UInt rD, ARMAMode1* am )
3041 vassert(rD <= 12);
3057 rD);
3086 UInt rD = iregEnc(i->ARMin.Alu.dst);
3104 (subopc << 1) & 0xF, rN, rD);
3114 UInt rD = iregEnc(i->ARMin.Shift.dst);
3124 instr |= XXXXX__X(X1110,X0001,X1010,X0000,rD, /* _ _ */ rM);
3139 case ARMun_NEG: /* RSB rD,rS,#0 */
3184 HReg rD;
3191 rD = i->ARMin.LdSt32.rD;
3197 rD = i->ARMin.LdSt8U.rD;
3214 iregEnc(rD));
3224 HReg rD = i->ARMin.LdSt16.rD;
3248 iregEnc(rD), imm8hi, X1011, imm8lo);
3255 iregEnc(rD), imm8hi, X1011, imm8lo);
3262 iregEnc(rD), imm8hi, X1111, imm8lo);
3273 HReg rD = i->ARMin.Ld8S.rD;
3293 iregEnc(rD), imm8hi, X1101, imm8lo);
4803 UInt regD = iregEnc(i->ARMin.Add32.rD);
