Lines Matching defs:MEM
212 #define ANNOTATE_EXPECT_RACE_FOR_MACHINE(mem, descr, machine) \
214 ANNOTATE_EXPECT_RACE(mem, descr); \
218 #define ANNOTATE_EXPECT_RACE_FOR_TSAN(mem, descr) \
219 ANNOTATE_EXPECT_RACE_FOR_MACHINE(mem, descr, "MSM_THREAD_SANITIZER")
229 // Initialize *(mem) to 0 if Tsan_FastMode.
230 #define FAST_MODE_INIT(mem) do { if (Tsan_FastMode()) { *(mem) = 0; } } while(0)
5023 // test104: TP. Simple race (write vs write). Heap mem. {{{1
5807 uint_union MEM[8];
5812 void Wr64_0() { MEM[0].u64[0] = 1; }
5813 void Wr64_1() { MEM[1].u64[0] = 1; }
5814 void Wr64_2() { MEM[2].u64[0] = 1; }
5815 void Wr64_3() { MEM[3].u64[0] = 1; }
5816 void Wr64_4() { MEM[4].u64[0] = 1; }
5817 void Wr64_5() { MEM[5].u64[0] = 1; }
5818 void Wr64_6() { MEM[6].u64[0] = 1; }
5819 void Wr64_7() { MEM[7].u64[0] = 1; }
5821 void Wr32_0() { MEM[0].u32[0] = 1; }
5822 void Wr32_1() { MEM[1].u32[1] = 1; }
5823 void Wr32_2() { MEM[2].u32[0] = 1; }
5824 void Wr32_3() { MEM[3].u32[1] = 1; }
5825 void Wr32_4() { MEM[4].u32[0] = 1; }
5826 void Wr32_5() { MEM[5].u32[1] = 1; }
5827 void Wr32_6() { MEM[6].u32[0] = 1; }
5828 void Wr32_7() { MEM[7].u32[1] = 1; }
5830 void Wr16_0() { MEM[0].u16[0] = 1; }
5831 void Wr16_1() { MEM[1].u16[1] = 1; }
5832 void Wr16_2() { MEM[2].u16[2] = 1; }
5833 void Wr16_3() { MEM[3].u16[3] = 1; }
5834 void Wr16_4() { MEM[4].u16[0] = 1; }
5835 void Wr16_5() { MEM[5].u16[1] = 1; }
5836 void Wr16_6() { MEM[6].u16[2] = 1; }
5837 void Wr16_7() { MEM[7].u16[3] = 1; }
5839 void Wr8_0() { MEM[0].u8[0] = 1; }
5840 void Wr8_1() { MEM[1].u8[1] = 1; }
5841 void Wr8_2() { MEM[2].u8[2] = 1; }
5842 void Wr8_3() { MEM[3].u8[3] = 1; }
5843 void Wr8_4() { MEM[4].u8[4] = 1; }
5844 void Wr8_5() { MEM[5].u8[5] = 1; }
5845 void Wr8_6() { MEM[6].u8[6] = 1; }
5846 void Wr8_7() { MEM[7].u8[7] = 1; }
5912 ANNOTATE_NEW_MEMORY(&MEM, sizeof(MEM));
5913 memset(&MEM, 0, sizeof(MEM));
5918 ANNOTATE_NEW_MEMORY(&MEM, sizeof(MEM));
5919 memset(&MEM, 0, sizeof(MEM));
