Lines Matching refs:GetCode
121 uint32_t GetCode() const { return (value_ & kCodeMask) >> kCodeShift; }
141 VIXL_ASSERT(GetCode() < kNumberOfRegisters);
143 bool Is(Register ref) const { return GetCode() == ref.GetCode(); }
144 bool IsLow() const { return GetCode() < kNumberOfT32LowRegisters; }
145 bool IsLR() const { return GetCode() == kLrCode; }
146 bool IsPC() const { return GetCode() == kPcCode; }
147 bool IsSP() const { return GetCode() == kSpCode; }
160 uint32_t GetCode() const { return code_; }
195 return ((GetCode() & 0x1) << single_bit_field) |
196 ((GetCode() & 0x1e) >> 1);
198 return ((GetCode() & 0x1) << single_bit_field) |
199 ((GetCode() & 0x1e) << (four_bit_field_lowest_bit - 1));
215 return os << "s" << reg.GetCode();
226 VIXL_ASSERT(GetCode() * lane_count < kNumberOfSRegisters);
227 return SRegister(GetCode() * lane_count + lane);
231 return ((GetCode() & 0x10) << (single_bit_field - 4)) |
232 ((GetCode() & 0xf) << four_bit_field_lowest_bit);
245 return os << "d" << reg.GetCode();
326 : DRegister(reg.GetCode()), lane_(lane) {}
333 uint32_t value = lane_ << ((dt.GetSize() == 16) ? 3 : 4) | GetCode();
356 os << "d" << lane.GetCode() << "[";
366 uint32_t Encode(int offset) { return GetCode() << offset; }
370 return DRegister(GetCode() * lane_count + lane);
372 DRegister GetLowDRegister() const { return DRegister(GetCode() * 2); }
373 DRegister GetHighDRegister() const { return DRegister(1 + GetCode() * 2); }
377 VIXL_ASSERT(GetCode() * lane_count < kNumberOfSRegisters);
378 return SRegister(GetCode() * lane_count + lane);
383 return ((GetCode() & 0x8) << (single_bit_field - 3)) |
384 ((GetCode() & 0x7) << (four_bit_field_lowest_bit + 1));
397 return os << "q" << reg.GetCode();
529 return UINT32_C(1) << reg.GetCode();
620 return UINT64_C(0xf) << (reg.GetCode() * 4);
622 return UINT64_C(0x3) << (reg.GetCode() * 2);
624 return UINT64_C(0x1) << reg.GetCode();
648 explicit SRegisterList(SRegister reg) : first_(reg.GetCode()), length_(1) {}
650 : first_(first.GetCode()), length_(length) {
656 return SRegister((first_.GetCode() + n) % kNumberOfSRegisters);
670 explicit DRegisterList(DRegister reg) : first_(reg.GetCode()), length_(1) {}
672 : first_(first.GetCode()), length_(length) {
678 return DRegister((first_.GetCode() + n) % kMaxNumberOfDRegisters);
700 : first_(reg.GetCode()),
708 : first_(reg.GetCode()),
719 : first_(first.GetCode()), spacing_(spacing), type_(type), lane_(-1) {
721 VIXL_ASSERT(first.GetCode() <= last.GetCode());
723 int range = last.GetCode() - first.GetCode();
733 : first_(first.GetCode()),
738 VIXL_ASSERT(first.GetCode() <= last.GetCode());
740 int range = last.GetCode() - first.GetCode();
749 unsigned code = first_.GetCode() + (IsDoubleSpaced() ? (2 * n) : n);
829 uint32_t GetCode() const { return reg_; }
942 uint32_t GetCode() const { return code_; }
947 return os << "c" << reg.GetCode();
