Lines Matching refs:out0
142 * Outputs - out0, out1, out2, out3
143 * Details : Load word in 'out0' from (psrc)
148 #define LW4(psrc, stride, out0, out1, out2, out3) do { \
150 out0 = LW(ptmp); \
213 * Outputs - out0, out1
215 * Details : Load 16 byte elements in 'out0' from (psrc)
218 #define LD_B2(RTYPE, psrc, stride, out0, out1) do { \
219 out0 = LD_B(RTYPE, psrc); \
225 #define LD_B3(RTYPE, psrc, stride, out0, out1, out2) do { \
226 LD_B2(RTYPE, psrc, stride, out0, out1); \
232 #define LD_B4(RTYPE, psrc, stride, out0, out1, out2, out3) do { \
233 LD_B2(RTYPE, psrc, stride, out0, out1); \
240 out0, out1, out2, out3, out4, out5, out6, out7) do { \
241 LD_B4(RTYPE, psrc, stride, out0, out1, out2, out3); \
249 * Outputs - out0, out1
250 * Details : Load 8 halfword elements in 'out0' from (psrc)
253 #define LD_H2(RTYPE, psrc, stride, out0, out1) do { \
254 out0 = LD_H(RTYPE, psrc); \
262 * Outputs - out0, out1, out2, out3
263 * Details : Load 4 word elements in 'out0' from (psrc + 0 * stride)
268 #define LD_W2(RTYPE, psrc, stride, out0, out1) do { \
269 out0 = LD_W(RTYPE, psrc); \
275 #define LD_W3(RTYPE, psrc, stride, out0, out1, out2) do { \
276 LD_W2(RTYPE, psrc, stride, out0, out1); \
282 #define LD_W4(RTYPE, psrc, stride, out0, out1, out2, out3) do { \
283 LD_W2(RTYPE, psrc, stride, out0, out1); \
423 * Outputs - out0, out1
426 * 'out0' as per control vector 'mask0'
436 #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) do { \
437 out0 = VSHF_B(RTYPE, in0, in1, mask0); \
447 * Outputs - out0, out1
450 * 'out0' as per control vector 'mask0'
452 #define VSHF_H2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) do { \
453 out0 = (RTYPE)__msa_vshf_h((v8i16)mask0, (v8i16)in1, (v8i16)in0); \
461 * Outputs - out0, out1
467 * are added together and written to the 'out0' vector
469 #define DOTP_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) do { \
470 out0 = (RTYPE)__msa_dotp_s_h((v16i8)mult0, (v16i8)cnst0); \
477 * Outputs - out0, out1
483 * are added together and written to the 'out0' vector
485 #define DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) do { \
486 out0 = (RTYPE)__msa_dotp_s_w((v8i16)mult0, (v8i16)cnst0); \
493 * Outputs - out0, out1
499 * are added together and written to the 'out0' vector
501 #define DOTP_UW2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) do { \
502 out0 = (RTYPE)__msa_dotp_u_d((v4u32)mult0, (v4u32)cnst0); \
509 * Outputs - out0, out1
515 * are added to the 'out0' vector
517 #define DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) do { \
518 out0 = (RTYPE)__msa_dpadd_s_w((v4i32)out0, (v8i16)mult0, (v8i16)cnst0); \
632 Outputs - out0, out1
636 halfword result is written in 'out0'
638 #define HADD_SH2(RTYPE, in0, in1, out0, out1) do { \
639 out0 = (RTYPE)__msa_hadd_s_w((v8i16)in0, (v8i16)in0); \
644 #define HADD_SH4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3) do { \
645 HADD_SH2(RTYPE, in0, in1, out0, out1); \
652 * Outputs - out0, out1
656 * halfword result is written to 'out0'
658 #define HSUB_UB2(RTYPE, in0, in1, out0, out1) do { \
659 out0 = (RTYPE)__msa_hsub_u_h((v16u8)in0, (v16u8)in0); \
705 * Outputs - out0, out1
708 * and written to 'out0'
710 #define ILVEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
711 out0 = (RTYPE)__msa_ilvev_b((v16i8)in1, (v16i8)in0); \
722 * Outputs - out0, out1
725 * and written to 'out0'
727 #define ILVOD_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
728 out0 = (RTYPE)__msa_ilvod_b((v16i8)in1, (v16i8)in0); \
739 * Outputs - out0, out1
742 * and written to 'out0'
744 #define ILVEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
745 out0 = (RTYPE)__msa_ilvev_h((v8i16)in1, (v8i16)in0); \
755 * Outputs - out0, out1
758 * and written to 'out0'
760 #define ILVOD_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
761 out0 = (RTYPE)__msa_ilvod_h((v8i16)in1, (v8i16)in0); \
771 * Outputs - out0, out1
774 * and written to 'out0'
776 #define ILVEV_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
777 out0 = (RTYPE)__msa_ilvev_w((v4i32)in1, (v4i32)in0); \
787 * Outputs - out0, out1
790 * and written to 'out0'
794 #define ILVEVOD_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
795 out0 = (RTYPE)__msa_ilvev_w((v4i32)in1, (v4i32)in0); \
805 * Outputs - out0, out1
808 * and written to 'out0'
812 #define ILVEVOD_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
813 out0 = (RTYPE)__msa_ilvev_h((v8i16)in1, (v8i16)in0); \
823 * Outputs - out0, out1
826 * and written to 'out0'
828 #define ILVEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
829 out0 = (RTYPE)__msa_ilvev_d((v2i64)in1, (v2i64)in0); \
839 * Outputs - out0, out1
842 * and written to 'out0'.
844 #define ILVL_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
845 out0 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \
856 * Outputs - out0, out1
859 * and written to out0.
861 #define ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
862 out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
872 out0, out1, out2, out3) do { \
873 ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
884 * Outputs - out0, out1
887 * interleaved and written to 'out0'.
889 #define ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
890 out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
898 out0, out1, out2, out3) do { \
899 ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1); \
908 * Outputs - out0, out1
911 * interleaved and written to 'out0'.
913 #define ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
914 out0 = (RTYPE)__msa_ilvr_d((v2i64)in0, (v2i64)in1); \
922 out0, out1, out2, out3) do { \
923 ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1); \
931 * Outputs - out0, out1
934 * interleaved and written to 'out0'
936 #define ILVRL_B2(RTYPE, in0, in1, out0, out1) do { \
937 out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
946 #define ILVRL_H2(RTYPE, in0, in1, out0, out1) do { \
947 out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
956 #define ILVRL_W2(RTYPE, in0, in1, out0, out1) do { \
957 out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \
967 * Outputs - out0, out1
970 * 'out0' & even byte elements of 'in1' are copied to the right
971 * half of 'out0'.
973 #define PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
974 out0 = (RTYPE)__msa_pckev_b((v16i8)in0, (v16i8)in1); \
983 out0, out1, out2, out3) do { \
984 PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
994 * Outputs - out0, out1
997 * 'out0' & even halfword elements of 'in1' are copied to the
998 * right half of 'out0'.
1000 #define PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1001 out0 = (RTYPE)__msa_pckev_h((v8i16)in0, (v8i16)in1); \
1011 * Outputs - out0, out1
1014 * 'out0' & even word elements of 'in1' are copied to the
1015 * right half of 'out0'.
1017 #define PCKEV_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1018 out0 = (RTYPE)__msa_pckev_w((v4i32)in0, (v4i32)in1); \
1028 * Outputs - out0, out1
1031 * 'out0' & odd halfword elements of 'in1' are copied to the
1032 * right half of 'out0'.
1034 #define PCKOD_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1035 out0 = (RTYPE)__msa_pckod_h((v8i16)in0, (v8i16)in1); \
1126 * Outputs - out0, out1
1128 * to 'out0'.
1130 #define ADDVI_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1131 out0 = (RTYPE)ADDVI_H(in0, in1); \
1139 * Outputs - out0, out1
1141 * to 'out0'.
1143 #define ADDVI_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1144 out0 = (RTYPE)ADDVI_W(in0, in1); \
1151 * Outputs - out0, out1
1152 * Details : GP register in0 is replicated in each word element of out0
1155 #define FILL_W2(RTYPE, in0, in1, out0, out1) do { \
1156 out0 = (RTYPE)__msa_fill_w(in0); \
1163 * Outputs - out0, out1
1165 * to 'out0'.
1167 #define ADD2(in0, in1, in2, in3, out0, out1) do { \
1168 out0 = in0 + in1; \
1173 out0, out1, out2, out3) do { \
1174 ADD2(in0, in1, in2, in3, out0, out1); \
1180 * Outputs - out0, out1
1182 * written to 'out0'.
1184 #define SUB2(in0, in1, in2, in3, out0, out1) do { \
1185 out0 = in0 - in1; \
1189 #define SUB3(in0, in1, in2, in3, in4, in5, out0, out1, out2) do { \
1190 out0 = in0 - in1; \
1196 out0, out1, out2, out3) do { \
1197 out0 = in0 - in1; \
1205 * Outputs - out0, out1
1207 * written to 'out0'.
1211 #define ADDSUB2(in0, in1, out0, out1) do { \
1212 out0 = in0 + in1; \
1218 * Outputs - out0, out1
1220 * and the result is written to 'out0'
1222 #define MUL2(in0, in1, in2, in3, out0, out1) do { \
1223 out0 = in0 * in1; \
1228 out0, out1, out2, out3) do { \
1229 MUL2(in0, in1, in2, in3, out0, out1); \
1249 * Outputs - out0, out1 (sign extended word vectors)
1253 * generate 4 signed word elements in 'out0'
1257 #define UNPCK_SH_SW(in, out0, out1) do { \
1259 ILVRL_H2_SW(tmp_m, in, out0, out1); \
1264 * Outputs - out0, out1, out2, out3
1267 #define BUTTERFLY_4(in0, in1, in2, in3, out0, out1, out2, out3) do { \
1268 out0 = in0 + in3; \
1277 * Outputs - out0, out1, out2, out3
1282 out0, out1, out2, out3) do { \
1291 ILVEVOD_H2_UB(tmp0_m, tmp1_m, tmp0_m, tmp1_m, out0, out2); \
1299 * Outputs - out0, out1, out2, out3, out4, out5, out6, out7
1304 out0, out1, out2, out3, out4, out5, \
1311 ILVEV_D2_UB(in6, in14, in7, in15, out1, out0); \
1314 ILVEV_B2_UB(out3, out2, out1, out0, out5, out7); \
1315 ILVOD_B2_SH(out3, out2, out1, out0, tmp6_m, tmp7_m); \
1317 ILVEVOD_W2_UB(tmp2_m, tmp3_m, tmp2_m, tmp3_m, out0, out4); \
1328 * Outputs - out0, out1, out2, out3
1332 out0, out1, out2, out3) do { \
1336 out0 = (RTYPE)__msa_ilvr_d((v2i64)s2_m, (v2i64)s0_m); \
1378 * Outputs - out0, out1
1382 * with rounding is calculated and written to 'out0'
1384 #define AVER_UB2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1385 out0 = (RTYPE)__msa_aver_u_b((v16u8)in0, (v16u8)in1); \
