Lines Matching refs:insn2
6215 /* Return the number of instructions that must separate INSN1 and INSN2,
6217 for any INSN2 if INSN2 is null. */
6221 const struct mips_cl_insn *insn2)
6229 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6246 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6256 if (insn2 == NULL
6257 || insn2->insn_opcode == INSN_ERET
6258 || insn2->insn_opcode == INSN_DERET
6259 || delayed_branch_p (insn2))
6285 if (insn2 == NULL)
6287 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6301 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6317 register. There must be a one instruction delay before INSN2
6318 if INSN2 reads that register, otherwise no delay is needed. */
6322 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6333 /* We don't know exactly what INSN1 does. If INSN2 is
6357 || (insn2 && delayed_branch_p (insn2))))
6405 #define BASE_REG_EQ(INSN1, INSN2) \
6407 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
