/external/valgrind/none/tests/mips64/ |
logical_instructions.c | 6 AND=0, ANDI, LUI, NOR, 27 case ANDI: 30 TEST2("andi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 31 TEST2("andi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 32 TEST2("andi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 33 TEST2("andi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); 34 TEST2("andi $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); 35 TEST2("andi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); 36 TEST2("andi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); 37 TEST2("andi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1) [all...] |
/external/pcre/dist2/src/sljit/ |
sljitNativeARM_64.c | 69 #define ANDI 0x92000000 598 return push_inst(compiler, (ANDI ^ inv_bits) | RD(dst) | RN(reg) | inst_bits); [all...] |
sljitNativeARM_T2_32.c | 99 #define ANDI 0xf0000000 617 return push_inst32(compiler, ANDI | (flags & SET_FLAGS) | RD4(dst) | RN4(reg) | nimm); [all...] |
sljitNativeMIPS_common.c | 103 #define ANDI (HI(12)) [all...] |
sljitNativePPC_common.c | 144 #define ANDI (HI(28)) [all...] |
/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.cpp | 432 mMips->ANDI(Rd, Rn, src); [all...] |