1 /** @file 2 3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4 Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR> 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef __ARM_LIB__ 17 #define __ARM_LIB__ 18 19 #include <Uefi/UefiBaseType.h> 20 21 #ifdef MDE_CPU_ARM 22 #include <Chipset/ArmV7.h> 23 #elif defined(MDE_CPU_AARCH64) 24 #include <Chipset/AArch64.h> 25 #else 26 #error "Unknown chipset." 27 #endif 28 29 /** 30 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes. 31 * 32 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only 33 * be used in Secure World to distinguished Secure to Non-Secure memory. 34 */ 35 typedef enum { 36 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, 37 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, 38 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, 39 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK, 40 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, 41 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH, 42 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, 43 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE 44 } ARM_MEMORY_REGION_ATTRIBUTES; 45 46 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1) 47 48 typedef struct { 49 EFI_PHYSICAL_ADDRESS PhysicalBase; 50 EFI_VIRTUAL_ADDRESS VirtualBase; 51 UINT64 Length; 52 ARM_MEMORY_REGION_ATTRIBUTES Attributes; 53 } ARM_MEMORY_REGION_DESCRIPTOR; 54 55 typedef VOID (*CACHE_OPERATION)(VOID); 56 typedef VOID (*LINE_OPERATION)(UINTN); 57 58 // 59 // ARM Processor Mode 60 // 61 typedef enum { 62 ARM_PROCESSOR_MODE_USER = 0x10, 63 ARM_PROCESSOR_MODE_FIQ = 0x11, 64 ARM_PROCESSOR_MODE_IRQ = 0x12, 65 ARM_PROCESSOR_MODE_SUPERVISOR = 0x13, 66 ARM_PROCESSOR_MODE_ABORT = 0x17, 67 ARM_PROCESSOR_MODE_HYP = 0x1A, 68 ARM_PROCESSOR_MODE_UNDEFINED = 0x1B, 69 ARM_PROCESSOR_MODE_SYSTEM = 0x1F, 70 ARM_PROCESSOR_MODE_MASK = 0x1F 71 } ARM_PROCESSOR_MODE; 72 73 // 74 // ARM Cpu IDs 75 // 76 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24) 77 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24) 78 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24) 79 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24) 80 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24) 81 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24) 82 83 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4) 84 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4) 85 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4) 86 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4) 87 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4) 88 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4) 89 90 // 91 // ARM MP Core IDs 92 // 93 #define ARM_CORE_AFF0 0xFF 94 #define ARM_CORE_AFF1 (0xFF << 8) 95 #define ARM_CORE_AFF2 (0xFF << 16) 96 #define ARM_CORE_AFF3 (0xFFULL << 32) 97 98 #define ARM_CORE_MASK ARM_CORE_AFF0 99 #define ARM_CLUSTER_MASK ARM_CORE_AFF1 100 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK) 101 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8) 102 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) 103 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) 104 105 UINTN 106 EFIAPI 107 ArmDataCacheLineLength ( 108 VOID 109 ); 110 111 UINTN 112 EFIAPI 113 ArmInstructionCacheLineLength ( 114 VOID 115 ); 116 117 UINTN 118 EFIAPI 119 ArmCacheWritebackGranule ( 120 VOID 121 ); 122 123 UINTN 124 EFIAPI 125 ArmIsArchTimerImplemented ( 126 VOID 127 ); 128 129 UINTN 130 EFIAPI 131 ArmReadIdPfr0 ( 132 VOID 133 ); 134 135 UINTN 136 EFIAPI 137 ArmReadIdPfr1 ( 138 VOID 139 ); 140 141 UINTN 142 EFIAPI 143 ArmCacheInfo ( 144 VOID 145 ); 146 147 BOOLEAN 148 EFIAPI 149 ArmIsMpCore ( 150 VOID 151 ); 152 153 VOID 154 EFIAPI 155 ArmInvalidateDataCache ( 156 VOID 157 ); 158 159 160 VOID 161 EFIAPI 162 ArmCleanInvalidateDataCache ( 163 VOID 164 ); 165 166 VOID 167 EFIAPI 168 ArmCleanDataCache ( 169 VOID 170 ); 171 172 VOID 173 EFIAPI 174 ArmInvalidateInstructionCache ( 175 VOID 176 ); 177 178 VOID 179 EFIAPI 180 ArmInvalidateDataCacheEntryByMVA ( 181 IN UINTN Address 182 ); 183 184 VOID 185 EFIAPI 186 ArmCleanDataCacheEntryToPoUByMVA( 187 IN UINTN Address 188 ); 189 190 VOID 191 EFIAPI 192 ArmCleanDataCacheEntryByMVA( 193 IN UINTN Address 194 ); 195 196 VOID 197 EFIAPI 198 ArmCleanInvalidateDataCacheEntryByMVA ( 199 IN UINTN Address 200 ); 201 202 VOID 203 EFIAPI 204 ArmInvalidateDataCacheEntryBySetWay ( 205 IN UINTN SetWayFormat 206 ); 207 208 VOID 209 EFIAPI 210 ArmCleanDataCacheEntryBySetWay ( 211 IN UINTN SetWayFormat 212 ); 213 214 VOID 215 EFIAPI 216 ArmCleanInvalidateDataCacheEntryBySetWay ( 217 IN UINTN SetWayFormat 218 ); 219 220 VOID 221 EFIAPI 222 ArmEnableDataCache ( 223 VOID 224 ); 225 226 VOID 227 EFIAPI 228 ArmDisableDataCache ( 229 VOID 230 ); 231 232 VOID 233 EFIAPI 234 ArmEnableInstructionCache ( 235 VOID 236 ); 237 238 VOID 239 EFIAPI 240 ArmDisableInstructionCache ( 241 VOID 242 ); 243 244 VOID 245 EFIAPI 246 ArmEnableMmu ( 247 VOID 248 ); 249 250 VOID 251 EFIAPI 252 ArmDisableMmu ( 253 VOID 254 ); 255 256 VOID 257 EFIAPI 258 ArmEnableCachesAndMmu ( 259 VOID 260 ); 261 262 VOID 263 EFIAPI 264 ArmDisableCachesAndMmu ( 265 VOID 266 ); 267 268 VOID 269 EFIAPI 270 ArmEnableInterrupts ( 271 VOID 272 ); 273 274 UINTN 275 EFIAPI 276 ArmDisableInterrupts ( 277 VOID 278 ); 279 280 BOOLEAN 281 EFIAPI 282 ArmGetInterruptState ( 283 VOID 284 ); 285 286 VOID 287 EFIAPI 288 ArmEnableAsynchronousAbort ( 289 VOID 290 ); 291 292 UINTN 293 EFIAPI 294 ArmDisableAsynchronousAbort ( 295 VOID 296 ); 297 298 VOID 299 EFIAPI 300 ArmEnableIrq ( 301 VOID 302 ); 303 304 UINTN 305 EFIAPI 306 ArmDisableIrq ( 307 VOID 308 ); 309 310 VOID 311 EFIAPI 312 ArmEnableFiq ( 313 VOID 314 ); 315 316 UINTN 317 EFIAPI 318 ArmDisableFiq ( 319 VOID 320 ); 321 322 BOOLEAN 323 EFIAPI 324 ArmGetFiqState ( 325 VOID 326 ); 327 328 /** 329 * Invalidate Data and Instruction TLBs 330 */ 331 VOID 332 EFIAPI 333 ArmInvalidateTlb ( 334 VOID 335 ); 336 337 VOID 338 EFIAPI 339 ArmUpdateTranslationTableEntry ( 340 IN VOID *TranslationTableEntry, 341 IN VOID *Mva 342 ); 343 344 VOID 345 EFIAPI 346 ArmSetDomainAccessControl ( 347 IN UINT32 Domain 348 ); 349 350 VOID 351 EFIAPI 352 ArmSetTTBR0 ( 353 IN VOID *TranslationTableBase 354 ); 355 356 VOID * 357 EFIAPI 358 ArmGetTTBR0BaseAddress ( 359 VOID 360 ); 361 362 RETURN_STATUS 363 EFIAPI 364 ArmConfigureMmu ( 365 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, 366 OUT VOID **TranslationTableBase OPTIONAL, 367 OUT UINTN *TranslationTableSize OPTIONAL 368 ); 369 370 BOOLEAN 371 EFIAPI 372 ArmMmuEnabled ( 373 VOID 374 ); 375 376 VOID 377 EFIAPI 378 ArmEnableBranchPrediction ( 379 VOID 380 ); 381 382 VOID 383 EFIAPI 384 ArmDisableBranchPrediction ( 385 VOID 386 ); 387 388 VOID 389 EFIAPI 390 ArmSetLowVectors ( 391 VOID 392 ); 393 394 VOID 395 EFIAPI 396 ArmSetHighVectors ( 397 VOID 398 ); 399 400 VOID 401 EFIAPI 402 ArmDataMemoryBarrier ( 403 VOID 404 ); 405 406 VOID 407 EFIAPI 408 ArmDataSynchronizationBarrier ( 409 VOID 410 ); 411 412 VOID 413 EFIAPI 414 ArmInstructionSynchronizationBarrier ( 415 VOID 416 ); 417 418 VOID 419 EFIAPI 420 ArmWriteVBar ( 421 IN UINTN VectorBase 422 ); 423 424 UINTN 425 EFIAPI 426 ArmReadVBar ( 427 VOID 428 ); 429 430 VOID 431 EFIAPI 432 ArmWriteAuxCr ( 433 IN UINT32 Bit 434 ); 435 436 UINT32 437 EFIAPI 438 ArmReadAuxCr ( 439 VOID 440 ); 441 442 VOID 443 EFIAPI 444 ArmSetAuxCrBit ( 445 IN UINT32 Bits 446 ); 447 448 VOID 449 EFIAPI 450 ArmUnsetAuxCrBit ( 451 IN UINT32 Bits 452 ); 453 454 VOID 455 EFIAPI 456 ArmCallSEV ( 457 VOID 458 ); 459 460 VOID 461 EFIAPI 462 ArmCallWFE ( 463 VOID 464 ); 465 466 VOID 467 EFIAPI 468 ArmCallWFI ( 469 470 VOID 471 ); 472 473 UINTN 474 EFIAPI 475 ArmReadMpidr ( 476 VOID 477 ); 478 479 UINTN 480 EFIAPI 481 ArmReadMidr ( 482 VOID 483 ); 484 485 UINT32 486 EFIAPI 487 ArmReadCpacr ( 488 VOID 489 ); 490 491 VOID 492 EFIAPI 493 ArmWriteCpacr ( 494 IN UINT32 Access 495 ); 496 497 VOID 498 EFIAPI 499 ArmEnableVFP ( 500 VOID 501 ); 502 503 /** 504 Get the Secure Configuration Register value 505 506 @return Value read from the Secure Configuration Register 507 508 **/ 509 UINT32 510 EFIAPI 511 ArmReadScr ( 512 VOID 513 ); 514 515 /** 516 Set the Secure Configuration Register 517 518 @param Value Value to write to the Secure Configuration Register 519 520 **/ 521 VOID 522 EFIAPI 523 ArmWriteScr ( 524 IN UINT32 Value 525 ); 526 527 UINT32 528 EFIAPI 529 ArmReadMVBar ( 530 VOID 531 ); 532 533 VOID 534 EFIAPI 535 ArmWriteMVBar ( 536 IN UINT32 VectorMonitorBase 537 ); 538 539 UINT32 540 EFIAPI 541 ArmReadSctlr ( 542 VOID 543 ); 544 545 UINTN 546 EFIAPI 547 ArmReadHVBar ( 548 VOID 549 ); 550 551 VOID 552 EFIAPI 553 ArmWriteHVBar ( 554 IN UINTN HypModeVectorBase 555 ); 556 557 558 // 559 // Helper functions for accessing CPU ACTLR 560 // 561 562 UINTN 563 EFIAPI 564 ArmReadCpuActlr ( 565 VOID 566 ); 567 568 VOID 569 EFIAPI 570 ArmWriteCpuActlr ( 571 IN UINTN Val 572 ); 573 574 VOID 575 EFIAPI 576 ArmSetCpuActlrBit ( 577 IN UINTN Bits 578 ); 579 580 VOID 581 EFIAPI 582 ArmUnsetCpuActlrBit ( 583 IN UINTN Bits 584 ); 585 586 RETURN_STATUS 587 ArmSetMemoryRegionNoExec ( 588 IN EFI_PHYSICAL_ADDRESS BaseAddress, 589 IN UINT64 Length 590 ); 591 592 RETURN_STATUS 593 ArmClearMemoryRegionNoExec ( 594 IN EFI_PHYSICAL_ADDRESS BaseAddress, 595 IN UINT64 Length 596 ); 597 598 RETURN_STATUS 599 ArmSetMemoryRegionReadOnly ( 600 IN EFI_PHYSICAL_ADDRESS BaseAddress, 601 IN UINT64 Length 602 ); 603 604 RETURN_STATUS 605 ArmClearMemoryRegionReadOnly ( 606 IN EFI_PHYSICAL_ADDRESS BaseAddress, 607 IN UINT64 Length 608 ); 609 610 #endif // __ARM_LIB__ 611
