1 /** @file 2 * 3 * Copyright (c) 2011-2015, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #ifndef __ARMGIC_H 16 #define __ARMGIC_H 17 18 #include <Library/ArmGicArchLib.h> 19 20 // 21 // GIC Distributor 22 // 23 #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register 24 #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register 25 #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register 26 27 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec) 28 #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers 29 #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers 30 #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers 31 #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers 32 #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers 33 #define ARM_GIC_ICDABR 0x300 // Active Bit Registers 34 35 // Each reg base below repeats for Number of interrupts / 4 36 #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers 37 38 // Each reg base below repeats for Number of interrupts 39 #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers 40 #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers 41 42 #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register 43 44 // just one of these 45 #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register 46 47 // GICv3 specific registers 48 #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers 49 50 // the Affinity Routing Enable (ARE) bit in GICD_CTLR 51 #define ARM_GIC_ICDDCR_ARE (1 << 4) 52 53 // 54 // GIC Redistributor 55 // 56 57 #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB 58 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB 59 60 // GIC Redistributor Control frame 61 #define ARM_GICR_TYPER 0x0008 // Redistributor Type Register 62 63 // GIC SGI & PPI Redistributor frame 64 #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers 65 #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers 66 67 // 68 // GIC Cpu interface 69 // 70 #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register 71 #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register 72 #define ARM_GIC_ICCBPR 0x08 // Binary Point Register 73 #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register 74 #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register 75 #define ARM_GIC_ICCRPR 0x14 // Running Priority Register 76 #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register 77 #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register 78 #define ARM_GIC_ICCIIDR 0xFC // Identification Register 79 80 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0 81 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1 82 #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2 83 84 // Bit-masks to configure the CPU Interface Control register 85 #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01 86 #define ARM_GIC_ICCICR_ENABLE_NS 0x02 87 #define ARM_GIC_ICCICR_ACK_CTL 0x04 88 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08 89 #define ARM_GIC_ICCICR_USE_SBPR 0x10 90 91 // Bit Mask for GICC_IIDR 92 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF) 93 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF) 94 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF) 95 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF) 96 97 // Bit Mask for 98 #define ARM_GIC_ICCIAR_ACKINTID 0x3FF 99 100 UINTN 101 EFIAPI 102 ArmGicGetInterfaceIdentification ( 103 IN INTN GicInterruptInterfaceBase 104 ); 105 106 // 107 // GIC Secure interfaces 108 // 109 VOID 110 EFIAPI 111 ArmGicSetupNonSecure ( 112 IN UINTN MpId, 113 IN INTN GicDistributorBase, 114 IN INTN GicInterruptInterfaceBase 115 ); 116 117 VOID 118 EFIAPI 119 ArmGicSetSecureInterrupts ( 120 IN UINTN GicDistributorBase, 121 IN UINTN* GicSecureInterruptMask, 122 IN UINTN GicSecureInterruptMaskSize 123 ); 124 125 VOID 126 EFIAPI 127 ArmGicEnableInterruptInterface ( 128 IN INTN GicInterruptInterfaceBase 129 ); 130 131 VOID 132 EFIAPI 133 ArmGicDisableInterruptInterface ( 134 IN INTN GicInterruptInterfaceBase 135 ); 136 137 VOID 138 EFIAPI 139 ArmGicEnableDistributor ( 140 IN INTN GicDistributorBase 141 ); 142 143 VOID 144 EFIAPI 145 ArmGicDisableDistributor ( 146 IN INTN GicDistributorBase 147 ); 148 149 UINTN 150 EFIAPI 151 ArmGicGetMaxNumInterrupts ( 152 IN INTN GicDistributorBase 153 ); 154 155 VOID 156 EFIAPI 157 ArmGicSendSgiTo ( 158 IN INTN GicDistributorBase, 159 IN INTN TargetListFilter, 160 IN INTN CPUTargetList, 161 IN INTN SgiId 162 ); 163 164 /* 165 * Acknowledge and return the value of the Interrupt Acknowledge Register 166 * 167 * InterruptId is returned separately from the register value because in 168 * the GICv2 the register value contains the CpuId and InterruptId while 169 * in the GICv3 the register value is only the InterruptId. 170 * 171 * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface 172 * @param InterruptId InterruptId read from the Interrupt Acknowledge Register 173 * 174 * @retval value returned by the Interrupt Acknowledge Register 175 * 176 */ 177 UINTN 178 EFIAPI 179 ArmGicAcknowledgeInterrupt ( 180 IN UINTN GicInterruptInterfaceBase, 181 OUT UINTN *InterruptId 182 ); 183 184 VOID 185 EFIAPI 186 ArmGicEndOfInterrupt ( 187 IN UINTN GicInterruptInterfaceBase, 188 IN UINTN Source 189 ); 190 191 UINTN 192 EFIAPI 193 ArmGicSetPriorityMask ( 194 IN INTN GicInterruptInterfaceBase, 195 IN INTN PriorityMask 196 ); 197 198 VOID 199 EFIAPI 200 ArmGicEnableInterrupt ( 201 IN UINTN GicDistributorBase, 202 IN UINTN GicRedistributorBase, 203 IN UINTN Source 204 ); 205 206 VOID 207 EFIAPI 208 ArmGicDisableInterrupt ( 209 IN UINTN GicDistributorBase, 210 IN UINTN GicRedistributorBase, 211 IN UINTN Source 212 ); 213 214 BOOLEAN 215 EFIAPI 216 ArmGicIsInterruptEnabled ( 217 IN UINTN GicDistributorBase, 218 IN UINTN GicRedistributorBase, 219 IN UINTN Source 220 ); 221 222 // 223 // GIC revision 2 specific declarations 224 // 225 226 // Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts) 227 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023)) 228 229 VOID 230 EFIAPI 231 ArmGicV2SetupNonSecure ( 232 IN UINTN MpId, 233 IN INTN GicDistributorBase, 234 IN INTN GicInterruptInterfaceBase 235 ); 236 237 VOID 238 EFIAPI 239 ArmGicV2EnableInterruptInterface ( 240 IN INTN GicInterruptInterfaceBase 241 ); 242 243 VOID 244 EFIAPI 245 ArmGicV2DisableInterruptInterface ( 246 IN INTN GicInterruptInterfaceBase 247 ); 248 249 UINTN 250 EFIAPI 251 ArmGicV2AcknowledgeInterrupt ( 252 IN UINTN GicInterruptInterfaceBase 253 ); 254 255 VOID 256 EFIAPI 257 ArmGicV2EndOfInterrupt ( 258 IN UINTN GicInterruptInterfaceBase, 259 IN UINTN Source 260 ); 261 262 // 263 // GIC revision 3 specific declarations 264 // 265 266 #define ICC_SRE_EL2_SRE (1 << 0) 267 268 #define ARM_GICD_IROUTER_IRM BIT31 269 270 UINT32 271 EFIAPI 272 ArmGicV3GetControlSystemRegisterEnable ( 273 VOID 274 ); 275 276 VOID 277 EFIAPI 278 ArmGicV3SetControlSystemRegisterEnable ( 279 IN UINT32 ControlSystemRegisterEnable 280 ); 281 282 VOID 283 EFIAPI 284 ArmGicV3EnableInterruptInterface ( 285 VOID 286 ); 287 288 VOID 289 EFIAPI 290 ArmGicV3DisableInterruptInterface ( 291 VOID 292 ); 293 294 UINTN 295 EFIAPI 296 ArmGicV3AcknowledgeInterrupt ( 297 VOID 298 ); 299 300 VOID 301 EFIAPI 302 ArmGicV3EndOfInterrupt ( 303 IN UINTN Source 304 ); 305 306 VOID 307 ArmGicV3SetBinaryPointer ( 308 IN UINTN BinaryPoint 309 ); 310 311 VOID 312 ArmGicV3SetPriorityMask ( 313 IN UINTN Priority 314 ); 315 316 #endif 317
