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      1 /* cris.h -- Header file for CRIS opcode and register tables.
      2    Copyright (C) 2000-2014 Free Software Foundation, Inc.
      3    Contributed by Axis Communications AB, Lund, Sweden.
      4    Originally written for GAS 1.38.1 by Mikael Asker.
      5    Updated, BFDized and GNUified by Hans-Peter Nilsson.
      6 
      7    This file is part of GAS, GDB and the GNU binutils.
      8 
      9    GAS, GDB, and GNU binutils is free software; you can redistribute it
     10    and/or modify it under the terms of the GNU General Public License as
     11    published by the Free Software Foundation; either version 3, or (at your
     12    option) any later version.
     13 
     14    GAS, GDB, and GNU binutils are distributed in the hope that they will be
     15    useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
     16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     17    GNU General Public License for more details.
     18 
     19    You should have received a copy of the GNU General Public License
     20    along with this program; if not, write to the Free Software
     21    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
     22    MA 02110-1301, USA.  */
     23 
     24 #ifndef __CRIS_H_INCLUDED_
     25 #define __CRIS_H_INCLUDED_
     26 
     27 #if !defined(__STDC__) && !defined(const)
     28 #define const
     29 #endif
     30 
     31 
     32 /* Registers.  */
     33 #define MAX_REG (15)
     34 #define REG_SP (14)
     35 #define REG_PC (15)
     36 
     37 /* CPU version control of disassembly and assembly of instructions.
     38    May affect how the instruction is assembled, at least the size of
     39    immediate operands.  */
     40 enum cris_insn_version_usage
     41 {
     42   /* Any version.  */
     43   cris_ver_version_all=0,
     44 
     45   /* Indeterminate (intended for disassembly only, or obsolete).  */
     46   cris_ver_warning,
     47 
     48   /* Only for v0..3 (Etrax 1..4).  */
     49   cris_ver_v0_3,
     50 
     51   /* Only for v3 or higher (ETRAX 4 and beyond).  */
     52   cris_ver_v3p,
     53 
     54   /* Only for v8 (Etrax 100).  */
     55   cris_ver_v8,
     56 
     57   /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX).  */
     58   cris_ver_v8p,
     59 
     60   /* Only for v0..10.  FIXME: Not sure what to do with this.  */
     61   cris_ver_sim_v0_10,
     62 
     63   /* Only for v0..10.  */
     64   cris_ver_v0_10,
     65 
     66   /* Only for v3..10.  (ETRAX 4, ETRAX 100 and ETRAX 100 LX).  */
     67   cris_ver_v3_10,
     68 
     69   /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX).  */
     70   cris_ver_v8_10,
     71 
     72   /* Only for v10 (ETRAX 100 LX) and same series.  */
     73   cris_ver_v10,
     74 
     75   /* Only for v10 (ETRAX 100 LX) and same series.  */
     76   cris_ver_v10p,
     77 
     78   /* Only for v32 or higher (codename GUINNESS).
     79      Of course some or all these of may change to cris_ver_v32p if/when
     80      there's a new revision. */
     81   cris_ver_v32p
     82 };
     83 
     84 
     85 /* Special registers.  */
     86 struct cris_spec_reg
     87 {
     88   const char *const name;
     89   unsigned int number;
     90 
     91   /* The size of the register.  */
     92   unsigned int reg_size;
     93 
     94   /* What CPU version the special register of that name is implemented
     95      in.  If cris_ver_warning, emit an unimplemented-warning.  */
     96   enum cris_insn_version_usage applicable_version;
     97 
     98   /* There might be a specific warning for using a special register
     99      here.  */
    100   const char *const warning;
    101 };
    102 extern const struct cris_spec_reg cris_spec_regs[];
    103 
    104 
    105 /* Support registers (kind of special too, but not named as such).  */
    106 struct cris_support_reg
    107 {
    108   const char *const name;
    109   unsigned int number;
    110 };
    111 extern const struct cris_support_reg cris_support_regs[];
    112 
    113 struct cris_cond15
    114 {
    115   /* The name of the condition.  */
    116   const char *const name;
    117 
    118   /* What CPU version this condition name applies to.  */
    119   enum cris_insn_version_usage applicable_version;
    120 };
    121 extern const struct cris_cond15 cris_conds15[];
    122 
    123 /* Opcode-dependent constants.  */
    124 #define AUTOINCR_BIT (0x04)
    125 
    126 /* Prefixes.  */
    127 #define BDAP_QUICK_OPCODE (0x0100)
    128 #define BDAP_QUICK_Z_BITS (0x0e00)
    129 
    130 #define BIAP_OPCODE	  (0x0540)
    131 #define BIAP_Z_BITS	  (0x0a80)
    132 
    133 #define DIP_OPCODE	  (0x0970)
    134 #define DIP_Z_BITS	  (0xf280)
    135 
    136 #define BDAP_INDIR_LOW	  (0x40)
    137 #define BDAP_INDIR_LOW_Z  (0x80)
    138 #define BDAP_INDIR_HIGH	  (0x09)
    139 #define BDAP_INDIR_HIGH_Z (0x02)
    140 
    141 #define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
    142 #define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
    143 #define BDAP_PC_LOW	  (BDAP_INDIR_LOW + REG_PC)
    144 #define BDAP_INCR_HIGH	  (BDAP_INDIR_HIGH + AUTOINCR_BIT)
    145 
    146 /* No prefix must have this code for its "match" bits in the
    147    opcode-table.  "BCC .+2" will do nicely.  */
    148 #define NO_CRIS_PREFIX 0
    149 
    150 /* Definitions for condition codes.  */
    151 #define CC_CC  0x0
    152 #define CC_HS  0x0
    153 #define CC_CS  0x1
    154 #define CC_LO  0x1
    155 #define CC_NE  0x2
    156 #define CC_EQ  0x3
    157 #define CC_VC  0x4
    158 #define CC_VS  0x5
    159 #define CC_PL  0x6
    160 #define CC_MI  0x7
    161 #define CC_LS  0x8
    162 #define CC_HI  0x9
    163 #define CC_GE  0xA
    164 #define CC_LT  0xB
    165 #define CC_GT  0xC
    166 #define CC_LE  0xD
    167 #define CC_A   0xE
    168 #define CC_EXT 0xF
    169 
    170 /* A table of strings "cc", "cs"... indexed with condition code
    171    values as above.  */
    172 extern const char *const cris_cc_strings[];
    173 
    174 /* Bcc quick.  */
    175 #define BRANCH_QUICK_LOW  (0)
    176 #define BRANCH_QUICK_HIGH (0)
    177 #define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
    178 #define BRANCH_QUICK_Z_BITS (0x0F00)
    179 
    180 /* BA quick.  */
    181 #define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
    182 #define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
    183 
    184 /* Bcc [PC+].  */
    185 #define BRANCH_PC_LOW	 (0xFF)
    186 #define BRANCH_INCR_HIGH (0x0D)
    187 #define BA_PC_INCR_OPCODE \
    188  ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
    189 
    190 /* Jump.  */
    191 /* Note that old versions generated special register 8 (in high bits)
    192    and not-that-old versions recognized it as a jump-instruction.
    193    That opcode now belongs to JUMPU.  */
    194 #define JUMP_INDIR_OPCODE (0x0930)
    195 #define JUMP_INDIR_Z_BITS (0xf2c0)
    196 #define JUMP_PC_INCR_OPCODE \
    197  (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
    198 
    199 #define MOVE_M_TO_PREG_OPCODE 0x0a30
    200 #define MOVE_M_TO_PREG_ZBITS 0x01c0
    201 
    202 /* BDAP.D N,PC.  */
    203 #define MOVE_PC_INCR_OPCODE_PREFIX \
    204  (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
    205 #define MOVE_PC_INCR_OPCODE_SUFFIX \
    206  (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
    207 
    208 #define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
    209 
    210 /* BA DWORD (V32).  */
    211 #define BA_DWORD_OPCODE (0x0EBF)
    212 
    213 /* Nop.  */
    214 #define NOP_OPCODE (0x050F)
    215 #define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
    216 
    217 #define NOP_OPCODE_V32 (0x05B0)
    218 #define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
    219 
    220 /* For the compatibility mode, let's use "MOVE R0,P0".  Doesn't affect
    221    registers or flags.  Unfortunately shuts off interrupts for one cycle
    222    for < v32, but there doesn't seem to be any alternative without that
    223    effect.  */
    224 #define NOP_OPCODE_COMMON (0x630)
    225 #define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
    226 
    227 /* LAPC.D  */
    228 #define LAPC_DWORD_OPCODE (0x0D7F)
    229 #define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
    230 
    231 /* Structure of an opcode table entry.  */
    232 enum cris_imm_oprnd_size_type
    233 {
    234   /* No size is applicable.  */
    235   SIZE_NONE,
    236 
    237   /* Always 32 bits.  */
    238   SIZE_FIX_32,
    239 
    240   /* Indicated by size of special register.  */
    241   SIZE_SPEC_REG,
    242 
    243   /* Indicated by size field, signed.  */
    244   SIZE_FIELD_SIGNED,
    245 
    246   /* Indicated by size field, unsigned.  */
    247   SIZE_FIELD_UNSIGNED,
    248 
    249   /* Indicated by size field, no sign implied.  */
    250   SIZE_FIELD
    251 };
    252 
    253 /* For GDB.  FIXME: Is this the best way to handle opcode
    254    interpretation?  */
    255 enum cris_op_type
    256 {
    257   cris_not_implemented_op = 0,
    258   cris_abs_op,
    259   cris_addi_op,
    260   cris_asr_op,
    261   cris_asrq_op,
    262   cris_ax_ei_setf_op,
    263   cris_bdap_prefix,
    264   cris_biap_prefix,
    265   cris_break_op,
    266   cris_btst_nop_op,
    267   cris_clearf_di_op,
    268   cris_dip_prefix,
    269   cris_dstep_logshift_mstep_neg_not_op,
    270   cris_eight_bit_offset_branch_op,
    271   cris_move_mem_to_reg_movem_op,
    272   cris_move_reg_to_mem_movem_op,
    273   cris_move_to_preg_op,
    274   cris_muls_op,
    275   cris_mulu_op,
    276   cris_none_reg_mode_add_sub_cmp_and_or_move_op,
    277   cris_none_reg_mode_clear_test_op,
    278   cris_none_reg_mode_jump_op,
    279   cris_none_reg_mode_move_from_preg_op,
    280   cris_quick_mode_add_sub_op,
    281   cris_quick_mode_and_cmp_move_or_op,
    282   cris_quick_mode_bdap_prefix,
    283   cris_reg_mode_add_sub_cmp_and_or_move_op,
    284   cris_reg_mode_clear_op,
    285   cris_reg_mode_jump_op,
    286   cris_reg_mode_move_from_preg_op,
    287   cris_reg_mode_test_op,
    288   cris_scc_op,
    289   cris_sixteen_bit_offset_branch_op,
    290   cris_three_operand_add_sub_cmp_and_or_op,
    291   cris_three_operand_bound_op,
    292   cris_two_operand_bound_op,
    293   cris_xor_op
    294 };
    295 
    296 struct cris_opcode
    297 {
    298   /* The name of the insn.  */
    299   const char *name;
    300 
    301   /* Bits that must be 1 for a match.  */
    302   unsigned int match;
    303 
    304   /* Bits that must be 0 for a match.  */
    305   unsigned int lose;
    306 
    307   /* See the table in "opcodes/cris-opc.c".  */
    308   const char *args;
    309 
    310   /* Nonzero if this is a delayed branch instruction.  */
    311   char delayed;
    312 
    313   /* Size of immediate operands.  */
    314   enum cris_imm_oprnd_size_type imm_oprnd_size;
    315 
    316   /* Indicates which version this insn was first implemented in.  */
    317   enum cris_insn_version_usage applicable_version;
    318 
    319   /* What kind of operation this is.  */
    320   enum cris_op_type op;
    321 };
    322 extern const struct cris_opcode cris_opcodes[];
    323 
    324 
    325 /* These macros are for the target-specific flags in disassemble_info
    326    used at disassembly.  */
    327 
    328 /* This insn accesses memory.  This flag is more trustworthy than
    329    checking insn_type for "dis_dref" which does not work for
    330    e.g. "JSR [foo]".  */
    331 #define CRIS_DIS_FLAG_MEMREF (1 << 0)
    332 
    333 /* The "target" field holds a register number.  */
    334 #define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
    335 
    336 /* The "target2" field holds a register number; add it to "target".  */
    337 #define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
    338 
    339 /* Yet another add-on: the register in "target2" must be multiplied
    340    by 2 before adding to "target".  */
    341 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
    342 
    343 /* Yet another add-on: the register in "target2" must be multiplied
    344    by 4 (mutually exclusive with .._MULT2).  */
    345 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
    346 
    347 /* The register in "target2" is an indirect memory reference (of the
    348    register there), add to "target".  Assumed size is dword (mutually
    349    exclusive with .._MULT[24]).  */
    350 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
    351 
    352 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
    353    sign-extended before adding to "target".  */
    354 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
    355 
    356 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
    357    sign-extended before adding to "target".  */
    358 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
    359 
    360 #endif /* __CRIS_H_INCLUDED_ */
    361 
    362 /*
    363  * Local variables:
    364  * eval: (c-set-style "gnu")
    365  * indent-tabs-mode: t
    366  * End:
    367  */
    368