| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 39 unsigned DstIdx;
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
106 unsigned getDstIdx() const { return DstIdx; }
|
| TwoAddressInstructionPass.cpp | 132 unsigned SrcIdx, unsigned DstIdx,
[all...] |
| RegisterCoalescer.cpp | 315 SrcIdx = DstIdx = 0;
362 SrcIdx, DstIdx);
371 DstIdx = SrcSub;
384 if (DstIdx && !SrcIdx) {
386 std::swap(SrcIdx, DstIdx);
405 std::swap(SrcIdx, DstIdx);
429 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
444 TRI.composeSubRegIndices(DstIdx, DstSub);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
84 assert(DstIdx != -1);
85 MachineOperand &DstOp = MI.getOperand(DstIdx);
|
| R600Packetizer.cpp | 92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
93 if (DstIdx == -1) {
96 unsigned Dst = BI->getOperand(DstIdx).getReg();
|
| R600ISelLowering.cpp | 223 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
224 assert(DstIdx != -1);
228 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) ||
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 126 unsigned SrcIdx, unsigned DstIdx,
864 unsigned SrcIdx, unsigned DstIdx, unsigned Dist
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
