| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 126 bool IsKill = false;
142 IsKill = true;
144 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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| MipsSERegisterInfo.cpp | 157 bool IsKill = false;
192 IsKill = true;
209 IsKill = true;
213 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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| MipsSEFrameLowering.cpp | 174 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
216 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
247 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
302 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
304 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
363 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
811 bool IsKill = !IsRAAndRetAddrIsTaken;
813 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 179 bool IsKill = false;
205 IsKill = true;
208 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
|
| HexagonBlockRanges.cpp | 318 bool IsKill = Op.isKill();
321 if (IsKill)
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| HexagonFrameLowering.cpp | [all...] |
| /external/libchrome/sandbox/linux/seccomp-bpf-helpers/ |
| syscall_sets.cc | 17 bool SyscallSets::IsKill(int sysno) {
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 419 bool IsKill = SrcDst->isKill();
473 SrcDstRegState |= getKillRegState(IsKill);
521 bool IsKill = MI->getOperand(0).isKill();
523 unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
535 .addReg(SubReg, getKillRegState(IsKill))
555 SuperKillState |= getKillRegState(IsKill);
[all...] |
| /external/llvm/lib/CodeGen/ |
| ScheduleDAGInstrs.cpp | 429 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
433 KillLaneMask = IsKill ? ~0u : DefLaneMask;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 826 bool IsKill = MO.isKill();
827 if (IsKill)
829 Regs.push_back(std::make_pair(Reg, IsKill));
[all...] |
