1 /** @file 2 * 3 * Copyright (c) 2012-2014, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #ifndef __LAN9118_DXE_HW_H__ 16 #define __LAN9118_DXE_HW_H__ 17 18 /*------------------------------------------------------------------------------ 19 LAN9118 SMCS Registers 20 ------------------------------------------------------------------------------*/ 21 22 // Base address as on the VE board 23 #define LAN9118_BA ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress)) 24 25 /* ------------- Tx and Rx Data and Status Memory Locations ------------------*/ 26 #define LAN9118_RX_DATA (0x00000000 + LAN9118_BA) 27 #define LAN9118_RX_STATUS (0x00000040 + LAN9118_BA) 28 #define LAN9118_RX_STATUS_PEEK (0x00000044 + LAN9118_BA) 29 #define LAN9118_TX_DATA (0x00000020 + LAN9118_BA) 30 #define LAN9118_TX_STATUS (0x00000048 + LAN9118_BA) 31 #define LAN9118_TX_STATUS_PEEK (0x0000004C + LAN9118_BA) 32 33 /* ------------- System Control and Status Registers -------------------------*/ 34 #define LAN9118_ID_REV (0x00000050 + LAN9118_BA) // Chip ID and Revision 35 #define LAN9118_IRQ_CFG (0x00000054 + LAN9118_BA) // Interrupt Configuration 36 #define LAN9118_INT_STS (0x00000058 + LAN9118_BA) // Interrupt Status 37 #define LAN9118_INT_EN (0x0000005C + LAN9118_BA) // Interrupt Enable 38 //#define LAN9118_RESERVED (0x00000060) 39 #define LAN9118_BYTE_TEST (0x00000064 + LAN9118_BA) // Byte Order Test 40 #define LAN9118_FIFO_INT (0x00000068 + LAN9118_BA) // FIFO Level Interrupts 41 #define LAN9118_RX_CFG (0x0000006C + LAN9118_BA) // Receive Configuration 42 #define LAN9118_TX_CFG (0x00000070 + LAN9118_BA) // Transmit Configuration 43 #define LAN9118_HW_CFG (0x00000074 + LAN9118_BA) // Hardware Configuration 44 #define LAN9118_RX_DP_CTL (0x00000078 + LAN9118_BA) // Receive Data-Path Configuration 45 #define LAN9118_RX_FIFO_INF (0x0000007C + LAN9118_BA) // Receive FIFO Information 46 #define LAN9118_TX_FIFO_INF (0x00000080 + LAN9118_BA) // Transmit FIFO Information 47 #define LAN9118_PMT_CTRL (0x00000084 + LAN9118_BA) // Power Management Control 48 #define LAN9118_GPIO_CFG (0x00000088 + LAN9118_BA) // General Purpose IO Configuration 49 #define LAN9118_GPT_CFG (0x0000008C + LAN9118_BA) // General Purpose Timer Configuration 50 #define LAN9118_GPT_CNT (0x00000090 + LAN9118_BA) // General Purpose Timer Current Count 51 #define LAN9118_WORD_SWAP (0x00000098 + LAN9118_BA) // Word Swap Control 52 #define LAN9118_FREE_RUN (0x0000009C + LAN9118_BA) // Free-Run 25MHz Counter 53 #define LAN9118_RX_DROP (0x000000A0 + LAN9118_BA) // Receiver Dropped Frames Counter 54 #define LAN9118_MAC_CSR_CMD (0x000000A4 + LAN9118_BA) // MAC CSR Synchronizer Command 55 #define LAN9118_MAC_CSR_DATA (0x000000A8 + LAN9118_BA) // MAC CSR Synchronizer Data 56 #define LAN9118_AFC_CFG (0x000000AC + LAN9118_BA) // Automatic Flow Control Configuration 57 #define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command 58 #define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data 59 60 61 // Receiver Status bits 62 #define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error 63 #define RXSTATUS_DB BIT2 // Dribbling bit: Frame had non-integer multiple of 8bits 64 #define RXSTATUS_MII_ERROR BIT3 // Receive error during interception 65 #define RXSTATUS_RXW_TO BIT4 // Incomming frame larger than 2kb 66 #define RXSTATUS_FT BIT5 // 1: Ether type / 0: 802.3 type frame 67 #define RXSTATUS_LCOLL BIT6 // Late collision detected 68 #define RXSTATUS_FTL BIT7 // Frame longer than Ether type 69 #define RXSTATUS_MCF BIT10 // Frame has Multicast Address 70 #define RXSTATUS_RUNT BIT11 // Bad frame 71 #define RXSTATUS_LE BIT12 // Actual length of frame different than it claims 72 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Address 73 #define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11 74 #define RXSTATUS_PL_MASK (0x3FFF0000) // Packet length bit mask 75 #define GET_RXSTATUS_PACKET_LENGTH(RxStatus) (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask 76 #define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test 77 78 // Transmitter Status bits 79 #define TXSTATUS_DEF BIT0 // Packet tx was deferred 80 #define TXSTATUS_EDEF BIT2 // Tx ended because of excessive deferral (> 24288 bit times) 81 #define TXSTATUS_CC_MASK (0x00000078) // Collision Count (before Tx) bit mask 82 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions) 83 #define TXSTATUS_LCOLL BIT9 // Packet Tx aborted after coll window of 64 bytes 84 #define TXSTATUS_NO_CA BIT10 // Carrier signal not present during Tx (bad?) 85 #define TXSTATUS_LOST_CA BIT11 // Lost carrier during Tx 86 #define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11 87 #define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for) 88 89 // ID_REV register bits 90 #define IDREV_ID ((MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16) 91 #define IDREV_REV (MmioRead32(LAN9118_ID_REV) & 0x0000FFFF) 92 93 // Interrupt Config Register bits 94 #define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type 95 #define IRQCFG_IRQ_POL BIT4 // IRQ Polarity 96 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 97 #define IRQCFG_IRQ_INT BIT12 // State of internal interrupts line 98 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval 99 #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter 100 #define IRQCFG_INT_DEAS_MASK (0xFF000000) // Interrupt deassertion interval value mask 101 102 // Interrupt Status Register bits 103 #define INSTS_GPIO_MASK (0x7) // GPIO interrupts mask 104 #define INSTS_RSFL (0x8) // Rx Status FIFO Level reached 105 #define INSTS_RSFF BIT4 // Rx Status FIFO full 106 #define INSTS_RXDF_INT BIT6 // Rx Frame dropped 107 #define INSTS_TSFL BIT7 // Tx Status FIFO Level reached 108 #define INSTS_TSFF BIT8 // Tx Status FIFO full 109 #define INSTS_TDFA BIT9 // Tx Data FIFO Level exceeded 110 #define INSTS_TDFO BIT10 // Tx Data FIFO full 111 #define INSTS_TXE BIT13 // Transmitter Error 112 #define INSTS_RXE BIT14 // Receiver Error 113 #define INSTS_RWT BIT15 // Packet > 2048 bytes received 114 #define INSTS_TXSO BIT16 // Tx Status FIFO Overflow 115 #define INSTS_PME_INT BIT17 // PME Signal detected 116 #define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt 117 #define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFFFF 118 #define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared 119 #define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO 120 #define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF 121 #define INSTS_RXSTOP_INT BIT24 // Rx was stopped 122 #define INSTS_TXSTOP_INT BIT25 // Tx was stopped 123 #define INSTS_SW_INT BIT31 // Software Interrupt occurred 124 125 // Interrupt Enable Register bits 126 127 128 // Hardware Config Register bits 129 #define HWCFG_SRST BIT0 // Software Reset bit (SC) 130 #define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO) 131 #define HWCFG_BMODE BIT2 // 32/16 bit Mode bit (RO) 132 #define HWCFG_TX_FIFO_SIZE_MASK (~ (UINT32)0xF0000) // Mask to Clear FIFO Size 133 #define HWCFG_MBO BIT20 // Must Be One bit 134 135 // Power Management Control Register 136 #define MPTCTRL_READY BIT0 // Device ready indicator 137 #define MPTCTRL_PME_EN BIT1 // Enable external PME signals 138 #define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals 139 #define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec) 140 #define MPTCTRL_WUPS_MASK (0x18) // Wake up status indicator mask 141 #define MPTCTRL_PME_TYPE BIT6 // PME Buffer type (Open Drain or Push-Pull) 142 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 143 #define MPTCTRL_WOL_EN BIT9 // Enable wake-on-lan 144 #define MPTCTRL_PHY_RST BIT10 // Reset the PHY 145 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode 146 147 // PHY control register bits 148 #define PHYCR_COLL_TEST BIT7 // Collision test enable 149 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 150 #define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities 151 #define PHYCR_PD BIT11 // Power-Down switch 152 #define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable 153 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection 154 #define PHYCR_LOOPBK BIT14 // Set loopback mode 155 #define PHYCR_RESET BIT15 // Do a PHY reset 156 157 // PHY status register bits 158 #define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability 159 #define PHYSTS_JABBER BIT1 // Jabber condition detected 160 #define PHYSTS_LINK_STS BIT2 // Link Status 161 #define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability 162 #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected 163 #define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed 164 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability 165 #define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability 166 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability 167 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability 168 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability 169 170 // PHY Auto-Negotiation advertisement 171 #define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector 172 #define PHYANA_10BASET BIT5 // Advertise 10BASET capability 173 #define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability 174 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability 175 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability 176 #define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability 177 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected 178 179 180 // PHY Auto-Negotiation Link Partner Ability 181 182 // PHY Auto-Negotiation Expansion 183 184 // PHY Mode control/status 185 186 // PHY Special Modes 187 188 // PHY Special control/status 189 190 // PHY Interrupt Source Flags 191 192 // PHY Interrupt Mask 193 194 // PHY Super Special control/status 195 #define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication 196 #define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done 197 198 199 // MAC control register bits 200 #define MACCR_RX_EN BIT2 // Enable Receiver bit 201 #define MACCR_TX_EN BIT3 // Enable Transmitter bit 202 #define MACCR_DFCHK BIT5 // Deferral Check bit 203 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 204 #define MACCR_BOLMT_MASK (0xC0) // Back-Off limit mask 205 #define MACCR_DISRTY BIT10 // Disable Transmit Retry bit 206 #define MACCR_BCAST BIT11 // Disable Broadcast Frames bit 207 #define MACCR_LCOLL BIT12 // Late Collision Control bit 208 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit 209 #define MACCR_HO BIT15 // Hash Only Filtering Mode 210 #define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit 211 #define MACCR_INVFILT BIT17 // Enable Inverse Filtering bit 212 #define MACCR_PRMS BIT18 // Promiscuous Mode bit 213 #define MACCR_MCPAS BIT19 // Pass all Multicast packets bit 214 #define MACCR_FDPX BIT20 // Full Duplex Mode bit 215 #define MACCR_LOOPBK BIT21 // Loopback operation mode bit 216 #define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit 217 #define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter 218 219 // Wake-Up Control and Status Register 220 #define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P) 221 #define WUCSR_WUEN BIT2 // Allow remote wake up using Wake-Up Frames 222 #define WUCSR_MPR_MASK (0x10) // Received Magic Packet 223 #define WUCSR_WUFR_MASK (0x20) // Received Wake-Up Frame 224 #define WUCSR_GUE BIT9 // Enable wake on global unicast frames 225 226 // RX Configuration Register bits 227 #define RXCFG_RXDOFF_MASK (0x1F00) // Rx Data Offset in Bytes 228 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs 229 #define RXCFG_RX_DMA_CNT_MASK (0x0FFF0000) // Amount of data to be read from Rx FIFO 230 #define RXCFG_RX_DMA_CNT(cnt) (((cnt) & 0xFFF) << 16) // Amount of data to be read from Rx FIFO 231 #define RXCFG_RX_END_ALIGN_MASK (0xC0000000) // Alignment to preserve 232 233 // TX Configuration Register bits 234 #define TXCFG_STOP_TX BIT0 // Stop the transmitter 235 #define TXCFG_TX_ON BIT1 // Start the transmitter 236 #define TXCFG_TXSAO BIT2 // Tx Status FIFO full 237 #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO 238 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO 239 240 // Rx FIFO Information Register bits 241 #define RXFIFOINF_RXDUSED_MASK (0xFFFF) // Rx Data FIFO Used Space 242 #define RXFIFOINF_RXSUSED_MASK (0xFF0000) // Rx Status FIFO Used Space 243 244 // Tx FIFO Information Register bits 245 #define TXFIFOINF_TDFREE_MASK (0xFFFF) // Tx Data FIFO Free Space 246 #define TXFIFOINF_TXSUSED_MASK (0xFF0000) // Tx Status FIFO Used Space 247 248 // E2P Register 249 #define E2P_EPC_BUSY BIT31 250 #define E2P_EPC_CMD_READ (0) 251 #define E2P_EPC_TIMEOUT BIT9 252 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8 253 #define E2P_EPC_ADDRESS(address) ((address) & 0xFFFF) 254 255 // GPIO Configuration register 256 #define GPIO_GPIO0_PUSH_PULL BIT16 257 #define GPIO_GPIO1_PUSH_PULL BIT17 258 #define GPIO_GPIO2_PUSH_PULL BIT18 259 #define GPIO_LED1_ENABLE BIT28 260 #define GPIO_LED2_ENABLE BIT29 261 #define GPIO_LED3_ENABLE BIT30 262 263 // MII_ACC bits 264 #define MII_ACC_MII_BUSY BIT0 265 #define MII_ACC_MII_WRITE BIT1 266 #define MII_ACC_MII_READ 0 267 268 #define MII_ACC_PHY_VALUE BIT11 269 #define MII_ACC_MII_REG_INDEX(index) (((index) & 0x1F) << 6) 270 271 // 272 // PHY Control Indexes 273 // 274 #define PHY_INDEX_BASIC_CTRL 0 275 #define PHY_INDEX_BASIC_STATUS 1 276 #define PHY_INDEX_ID1 2 277 #define PHY_INDEX_ID2 3 278 #define PHY_INDEX_AUTO_NEG_ADVERT 4 279 #define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5 280 #define PHY_INDEX_AUTO_NEG_EXP 6 281 #define PHY_INDEX_MODE 17 282 #define PHY_INDEX_SPECIAL_MODES 18 283 #define PHY_INDEX_SPECIAL_CTLR 27 284 #define PHY_INDEX_INT_SRC 29 285 #define PHY_INDEX_INT_MASK 30 286 #define PHY_INDEX_SPECIAL_PHY_CTLR 31 287 288 // Indirect MAC Indexes 289 #define INDIRECT_MAC_INDEX_CR 1 290 #define INDIRECT_MAC_INDEX_ADDRH 2 291 #define INDIRECT_MAC_INDEX_ADDRL 3 292 #define INDIRECT_MAC_INDEX_HASHH 4 293 #define INDIRECT_MAC_INDEX_HASHL 5 294 #define INDIRECT_MAC_INDEX_MII_ACC 6 295 #define INDIRECT_MAC_INDEX_MII_DATA 7 296 297 // 298 // MAC CSR Synchronizer Command register 299 // 300 #define MAC_CSR_BUSY BIT31 301 #define MAC_CSR_READ BIT30 302 #define MAC_CSR_WRITE 0 303 #define MAC_CSR_ADDR(Addr) ((Addr) & 0xFF) 304 305 // 306 // TX Packet Format 307 // 308 #define TX_CMD_A_COMPLETION_INT BIT31 309 #define TX_CMD_A_FIRST_SEGMENT BIT13 310 #define TX_CMD_A_LAST_SEGMENT BIT12 311 #define TX_CMD_A_BUFF_SIZE(size) ((size) & 0x000003FF) 312 #define TX_CMD_A_DATA_START_OFFSET(offset) (((offset) & 0x1F) << 16) 313 #define TX_CMD_B_PACKET_LENGTH(size) ((size) & 0x000003FF) 314 #define TX_CMD_B_PACKET_TAG(tag) (((tag) & 0x3FF) << 16) 315 316 // Hardware Configuration Register 317 #define HW_CFG_TX_FIFO_SIZE_MASK (0xF << 16) 318 #define HW_CFG_TX_FIFO_SIZE(size) (((size) & 0xF) << 16) 319 320 // EEPROM Definition 321 #define EEPROM_EXTERNAL_SERIAL_EEPROM 0xA5 322 323 // 324 // Conditional compilation flags 325 // 326 //#define EVAL_PERFORMANCE 327 328 329 #endif /* __LAN9118_DXE_HDR_H__ */ 330
