| /external/v8/src/crankshaft/arm64/ |
| delayed-masm-arm64-inl.h | 23 void DelayedMasm::Mov(const Register& rd,
28 __ Mov(rd, operand, discard_mode);
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 86 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
91 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
94 Mov->getOperand(MovPredSelIdx).setReg(
|
| SIRegisterInfo.cpp | 544 MachineInstrBuilder Mov
556 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState);
[all...] |
| AMDGPUISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceVariableSplitting.cpp | 316 Inst *Mov = Target->createLoweredMove(NewMapped, Dest);
317 Node->getInsts().insert(IterNext, Mov);
341 Inst *Mov = Target->createLoweredMove(NewMapped, SrcVar);
342 Node->getInsts().insert(IterNext, Mov);
347 Inst *Mov = Target->createLoweredMove(OldMapped, SrcVar);
348 Mov->setDestRedefined();
349 Node->getInsts().insert(IterNext, Mov);
366 Inst *Mov = Target->createLoweredMove(NewMapped, Dest);
367 Node->getInsts().insert(IterCur, Mov);
400 Inst *Mov = Target->createLoweredMove(NewMapped, OldMapped)
[all...] |
| IceInstARM32.h | 403 Mov,
[all...] |
| IceInstMIPS32.h | 235 Mov, // actually a pseudo op for addi rd, rs, 0
[all...] |
| IceInstX86Base.h | 120 Mov,
319 /// mov c, x
322 /// mov c, y
326 /// intra-block control flow, liveness analysis will determine the "mov c, x"
328 /// "FakeUse(c)" instruction anywhere between the two "mov c, ..."
333 /// mov c, x
337 /// mov c, y
340 /// The down-side is that "mov c, x" can never be dead-code eliminated even if
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 673 MachineInstrBuilder Mov =
679 Mov->addRegisterDefined(DestReg, TRI);
681 Mov->addRegisterKilled(SrcReg, TRI);
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 219 Mov(rd, -operand.ImmediateValue());
290 Mov(rd, ~imm);
772 Mov(tmp, float_to_rawbits(imm));
956 void MacroAssembler::Mov(const Register& rd, const Register& rn) {
960 // not X registers. Note that mov(w0, w0) is not a no-op because it clears
963 Assembler::mov(rd, rn);
[all...] |
| macro-assembler-arm64.cc | 90 Mov(rd, 0);
94 Mov(rd, rn);
106 Mov(rd, rn);
109 Mov(rd, immediate);
134 Mov(csp, temp);
161 void MacroAssembler::Mov(const Register& rd, uint64_t imm) {
203 // Mov instructions can't move immediate values into the stack pointer, so
233 mov(rd, temp);
240 void MacroAssembler::Mov(const Register& rd,
256 Mov(dst, operand.ImmediateValue())
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | 406 // The worst case for size is mov 64-bit immediate to sp:
449 // Mov instructions can't move values into the stack pointer, so set up a
487 if (emit_code) masm->mov(rd, temp);
795 Mov(rd, 0);
800 Mov(rd, rn);
813 Mov(rd, rn);
816 Mov(rd, immediate);
843 Mov(sp, temp);
872 void MacroAssembler::Mov(const Register& rd,
876 // The worst case for size is mov immediate with up to 4 instructions
[all...] |
| macro-assembler-aarch64.h | 602 // instruction using 'mov immediate' instructions. A user might prefer loading
603 // a constant using the literal pool instead of using multiple 'mov immediate'
664 void Mov(const Register& rd, uint64_t imm);
665 void Mov(const Register& rd,
669 Mov(rd, (rd.GetSizeInBits() == kXRegSize) ? ~imm : (~imm & kWRegMask));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 818 MachineInstrBuilder Mov;
836 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
839 Mov.addReg(Src);
840 Mov = AddDefaultPred(Mov);
843 Mov = AddDefaultCC(Mov);
846 Mov->addRegisterDefined(DestReg, TRI);
848 Mov->addRegisterKilled(SrcReg, TRI);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm_defs.h | 660 /* MOV dst, src -- reg-reg (or reg-imm8x4) move */
664 } Mov;
722 /* Mov src to dst on the given condition, which may not
809 /* 64-bit FP mov src to dst on the given condition, which may
816 /* 32-bit FP mov src to dst on the given condition, which may
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
