/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
omxVCM4P2_MCReconBlock_s.s | 299 LCLS OP2 302 OP2 SETS "ORR" 305 OP2 SETS "AND" 318 $OP2 $lsb2, $lsb2, $lsb0 ;// e2 = e2 | e0
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/toolchain/binutils/binutils-2.25/include/opcode/ |
sparc.h | 251 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 260 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG1, OWREG2) [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600Defines.h | 42 OP2 = (1 << 11),
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/toolchain/binutils/binutils-2.25/gas/config/ |
tc-rx.c | [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
aarch64-tbl.h | 29 #define OP2(a,b) {OPND(a), OPND(b)} 55 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ 61 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ 1240 {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF}, 1242 {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF}, 1246 {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF}, 1249 {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF}, 1252 {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF}, 1254 {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF}, 1257 {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF} [all...] |
/external/pcre/dist2/src/ |
pcre2_jit_compile.c | 557 #define OP2(op, dst, dstw, src1, src1w, src2, src2w) \ [all...] |