| /toolchain/binutils/binutils-2.25/include/opcode/ |
| sparc.h | 252 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
257 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
258 #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
261 #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
|
| tic6x-opcode-table.h | 44 #define OP3(a, b, c) 3, { a, b, c }
162 OP3(ORREG1, ORXREG1, OWREG1),
167 OP3(ORREG1, ORXREG1, OWREGL1),
172 OP3(ORXREG1, ORREGL1, OWREGL1),
177 OP3(OACST, ORXREG1, OWREG1),
182 OP3(OACST, ORREGL1, OWREGL1),
187 OP3(ORREG1, ORXREG1, OWREG1),
192 OP3(OACST, ORXREG1, OWREG1),
198 OP3(ORREG1, ORREG1, OWREG1),
204 OP3(ORREG1, OACST, OWREG1)
[all...] |
| h8300.h | 103 OP3 = 0x40000,
141 R3_8 = OP3 | L_8 | REG,
142 R3_16 = OP3 | L_16 | REG,
143 R3_32 = OP3 | L_32 | REG,
154 OP3PCREL8 = OP3 | PCREL | L_8,
155 OP3PCREL16 = OP3 | PCREL | L_16,
192 ABS8OP3 = OP3 | ABS | L_8,
193 ABS16OP3 = OP3 | ABS | L_16U,
194 ABS24OP3 = OP3 | ABS | L_24,
195 ABS32OP3 = OP3 | ABS | L_32
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600Defines.h | 37 OP3 = (1 << 5),
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-rx.c | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-tbl.h | 30 #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
1237 {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1238 {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1239 {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1241 {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1244 {"add", 0x0b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
1245 {"adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
1247 {"sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
1248 {"subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
1251 {"add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}
[all...] |
