/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyFastISel.cpp | 948 EVT RetVT = TLI.getValueType(DL, I->getType()); 949 if (!VT.isSimple() || !RetVT.isSimple()) 952 if (VT == RetVT) { 958 unsigned Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeFloatTypes.cpp | 680 EVT RetVT = TLI.getCmpLibcallReturnType(); 682 NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl); 683 NewRHS = DAG.getConstant(0, RetVT); 686 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), 688 NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/, dl); 689 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS, [all...] |
LegalizeVectorTypes.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsFastISel.cpp | 153 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS, 197 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes); 246 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCFastISel.cpp | 188 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMFastISel.cpp | 143 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT, 199 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 461 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT, 464 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | 153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT); 158 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS, 161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, 164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, 167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, 172 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, 181 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt); 182 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm); 183 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS); 190 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | 200 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, [all...] |
/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | 119 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I); 121 bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I); 123 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I); 276 MVT RetVT; 280 if (!isTypeLegal(RetTy, RetVT)) 283 if (RetVT != MVT::i32 && RetVT != MVT::i64) [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorTypes.cpp | [all...] |
TargetLowering.cpp | 115 /// result of type RetVT. 117 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, 138 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 140 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned); 253 EVT RetVT = getCmpLibcallReturnType(); 255 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, false /*sign irrelevant*/, 257 NewRHS = DAG.getConstant(0, dl, RetVT); 266 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT), 268 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, false/*sign irrelevant*/, 272 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT), [all...] |