1 /*++ 2 3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> 4 5 This program and the accompanying materials are licensed and made available under 7 the terms and conditions of the BSD License that accompanies this distribution. 9 The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php. 13 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 19 21 **/ 23 24 #ifndef _SPIFlash_H_ 25 #define _SPIFlash_H_ 26 27 #include <Protocol/Spi.h> 28 29 //EFI_STATUS SpiFlashLock(BOOLEAN Lock); 30 //EFI_STATUS SpiFlashInit(void); 31 32 typedef enum { 33 EnumSpiFlashW25Q64, 34 EnumSpiFlashAT25DF321A, 35 EnumSpiFlashAT26DF321, 36 EnumSpiFlashAT25DF641, 37 EnumSpiFlashW25Q16, 38 EnumSpiFlashW25Q32, 39 EnumSpiFlashW25X32, 40 EnumSpiFlashW25X64, 41 EnumSpiFlashW25Q128, 42 EnumSpiFlashMX25L16, 43 EnumSpiFlashMX25L32, 44 EnumSpiFlashMX25L64, 45 EnumSpiFlashMX25L128, 46 EnumSpiFlashMX25U6435F, 47 EnumSpiFlashSST25VF016B, 48 EnumSpiFlashSST25VF064C, 49 EnumSpiFlashN25Q064, 50 EnumSpiFlashM25PX16, 51 EnumSpiFlashN25Q032, 52 EnumSpiFlashM25PX32, 53 EnumSpiFlashM25PX64, 54 EnumSpiFlashN25Q128, 55 EnumSpiFlashEN25Q16, 56 EnumSpiFlashEN25Q32, 57 EnumSpiFlashEN25Q64, 58 EnumSpiFlashEN25Q128, 59 EnumSpiFlashA25L016, 60 EnumSpiFlashMax 61 } SPI_FLASH_TYPES_SUPPORTED; 62 63 // 64 // Serial Flash VendorId and DeviceId 65 // 66 #define SF_VENDOR_ID_ATMEL 0x1F 67 #define SF_DEVICE_ID0_AT26DF321 0x47 68 #define SF_DEVICE_ID1_AT26DF321 0x00 69 #define SF_DEVICE_ID0_AT25DF321A 0x47 70 #define SF_DEVICE_ID1_AT25DF321A 0x01 71 #define SF_DEVICE_ID0_AT25DF641 0x48 72 #define SF_DEVICE_ID1_AT25DF641 0x00 73 74 #define SF_VENDOR_ID_WINBOND 0xEF 75 #define SF_DEVICE_ID0_W25XXX 0x30 76 #define SF_DEVICE_ID1_W25X32 0x16 77 #define SF_DEVICE_ID1_W25X64 0x17 78 #define SF_DEVICE_ID0_W25QXX 0x40 79 #define SF_DEVICE_ID1_W25Q16 0x15 80 #define SF_DEVICE_ID1_W25Q32 0x16 81 #define SF_DEVICE_ID1_W25Q64 0x17 82 #define SF_DEVICE_ID1_W25Q128 0x18 83 84 #define SF_VENDOR_ID_MACRONIX 0xC2 85 #define SF_DEVICE_ID0_MX25LXX 0x20 86 #define SF_DEVICE_ID1_MX25L16 0x15 87 #define SF_DEVICE_ID1_MX25L32 0x16 88 #define SF_DEVICE_ID1_MX25L64 0x17 89 #define SF_DEVICE_ID1_MX25L128 0x18 90 #define SF_DEVICE_ID0_MX25UXX 0x25 91 #define SF_DEVICE_ID1_MX25U6435F 0x37 92 93 #define SF_VENDOR_ID_NUMONYX 0x20 94 #define SF_DEVICE_ID0_N25Q064 0xBB 95 #define SF_DEVICE_ID1_N25Q064 0x17 96 #define SF_DEVICE_ID0_M25PXXX 0x71 97 #define SF_DEVICE_ID0_N25QXXX 0xBA 98 #define SF_DEVICE_ID1_M25PX16 0x15 99 #define SF_DEVICE_ID1_N25Q032 0x16 100 #define SF_DEVICE_ID1_M25PX32 0x16 101 #define SF_DEVICE_ID1_M25PX64 0x17 102 #define SF_DEVICE_ID1_N25Q128 0x18 103 104 #define SF_VENDOR_ID_SST 0xBF 105 #define SF_DEVICE_ID0_SST25VF0XXX 0x25 106 #define SF_DEVICE_ID1_SST25VF016B 0x41 107 #define SF_DEVICE_ID1_SST25VF064C 0x4B 108 109 #define SF_VENDOR_ID_EON 0x1C 110 #define SF_DEVICE_ID0_EN25QXX 0x30 111 #define SF_DEVICE_ID1_EN25Q16 0x15 112 #define SF_DEVICE_ID1_EN25Q32 0x16 113 #define SF_DEVICE_ID1_EN25Q64 0x17 114 #define SF_DEVICE_ID1_EN25Q128 0x18 115 116 #define SF_VENDOR_ID_AMIC 0x37 117 #define SF_DEVICE_ID0_A25L016 0x30 118 #define SF_DEVICE_ID1_A25L016 0x15 119 120 #define ATMEL_AT26DF321_SIZE 0x00400000 121 #define ATMEL_AT25DF321A_SIZE 0x00400000 122 #define ATMEL_AT25DF641_SIZE 0x00800000 123 #define WINBOND_W25X32_SIZE 0x00400000 124 #define WINBOND_W25X64_SIZE 0x00800000 125 #define WINBOND_W25Q16_SIZE 0x00200000 126 #define WINBOND_W25Q32_SIZE 0x00400000 127 #define WINBOND_W25Q64_SIZE 0x00800000 128 #define WINBOND_W25Q128_SIZE 0x01000000 129 #define SST_SST25VF016B_SIZE 0x00200000 130 #define SST_SST25VF064C_SIZE 0x00800000 131 #define MACRONIX_MX25L16_SIZE 0x00200000 132 #define MACRONIX_MX25L32_SIZE 0x00400000 133 #define MACRONIX_MX25L64_SIZE 0x00800000 134 #define MACRONIX_MX25U64_SIZE 0x00800000 135 #define MACRONIX_MX25L128_SIZE 0x01000000 136 #define NUMONYX_M25PX16_SIZE 0x00400000 137 #define NUMONYX_N25Q032_SIZE 0x00400000 138 #define NUMONYX_M25PX32_SIZE 0x00400000 139 #define NUMONYX_M25PX64_SIZE 0x00800000 140 #define NUMONYX_N25Q064_SIZE 0x00800000 141 #define NUMONYX_N25Q128_SIZE 0x01000000 142 #define EON_EN25Q16_SIZE 0x00200000 143 #define EON_EN25Q32_SIZE 0x00400000 144 #define EON_EN25Q64_SIZE 0x00800000 145 #define EON_EN25Q128_SIZE 0x01000000 146 #define AMIC_A25L16_SIZE 0x00200000 147 148 #define SF_VENDOR_ID_SST 0xBF 149 #define SF_DEVICE_ID0_25LF080A 0x25 150 #define SF_DEVICE_ID1_25LF080A 0x8E 151 #define SF_DEVICE_ID0_25VF016B 0x25 152 #define SF_DEVICE_ID1_25VF016B 0x41 153 154 #define SF_VENDOR_ID_ATMEL 0x1F 155 #define SF_DEVICE_ID0_AT26DF321 0x47 156 #define SF_DEVICE_ID1_AT26DF321 0x00 157 158 #define SF_VENDOR_ID_STM 0x20 159 #define SF_DEVICE_ID0_M25P32 0x20 160 #define SF_DEVICE_ID1_M25P32 0x16 161 162 #define SF_VENDOR_ID_WINBOND 0xEF 163 #define SF_DEVICE_ID0_W25XXX 0x30 164 165 #define SF_DEVICE_ID1_W25X80 0x14 166 #define SF_DEVICE_ID1_W25X16 0x15 167 #define SF_DEVICE_ID1_W25X32 0x16 168 #define SF_DEVICE_ID1_W25X64 0x17 169 170 #define SF_VENDOR_ID_MX 0xC2 171 #define SF_DEVICE_ID0_25L1605A 0x20 172 #define SF_DEVICE_ID1_25L1605A 0x15 173 174 #define SF_VENDOR_ID_NUMONYX 0x20 175 #define SF_DEVICE_ID0_M25PX16 0x71 176 #define SF_DEVICE_ID1_M25PX16 0x15 177 178 #define SST_25LF080A_SIZE 0x00100000 179 #define SST_25LF016B_SIZE 0x00200000 180 #define ATMEL_AT26DF321_SIZE 0x00400000 181 #define STM_M25P32_SIZE 0x00400000 182 #define WINBOND_W25X80_SIZE 0x00100000 183 #define WINBOND_W25X16_SIZE 0x00200000 184 #define WINBOND_W25X32_SIZE 0x00400000 185 #define WINBOND_W25X64_SIZE 0x00800000 186 #define MX_25L1605A_SIZE 0x00200000 187 188 // 189 // Physical Sector Size on the Serial Flash device 190 // 191 #define SF_SECTOR_SIZE 0x1000 192 #define SF_BLOCK_SIZE 0x8000 193 194 // 195 // Serial Flash Status Register definitions 196 // 197 #define SF_SR_BUSY 0x01 // Indicates if internal write operation is in progress 198 #define SF_SR_WEL 0x02 // Indicates if device is memory write enabled 199 #define SF_SR_BP0 0x04 // Block protection bit 0 200 #define SF_SR_BP1 0x08 // Block protection bit 1 201 #define SF_SR_BP2 0x10 // Block protection bit 2 202 #define SF_SR_BP3 0x20 // Block protection bit 3 203 #define SF_SR_WPE 0x3C // Enable write protection on all blocks 204 #define SF_SR_AAI 0x40 // Auto Address Increment Programming status 205 #define SF_SR_BPL 0x80 // Block protection lock-down 206 207 // 208 // Operation Instruction definitions for the Serial Flash Device 209 // 210 #define SF_INST_WRSR 0x01 // Write Status Register 211 #define SF_INST_PROG 0x02 // Byte Program 212 #define SF_INST_READ 0x03 // Read 213 #define SF_INST_WRDI 0x04 // Write Disable 214 #define SF_INST_RDSR 0x05 // Read Status Register 215 #define SF_INST_WREN 0x06 // Write Enable 216 #define SF_INST_HS_READ 0x0B // High-speed Read 217 #define SF_INST_SERASE 0x20 // Sector Erase (4KB) 218 #define SF_INST_BERASE 0x52 // Block Erase (32KB) 219 #define SF_INST_64KB_ERASE 0xD8 // Block Erase (64KB) 220 #define SF_INST_EWSR 0x50 // Enable Write Status Register 221 #define SF_INST_READ_ID 0xAB // Read ID 222 #define SF_INST_JEDEC_READ_ID 0x9F // JEDEC Read ID 223 #define SF_INST_DOFR 0x3B // Dual Output Fast Read 224 #define SF_INST_SFDP 0x5A // Serial Flash Discovery Parameters 225 226 #define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size 227 #define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size 228 #define BLOCK_SIZE_64KB 0x00010000 // Common 64kBytes block size 229 #define MAX_FWH_SIZE 0x00100000 // 8Mbit (Note that this can also be used for the 4Mbit ) 230 231 // 232 // Prefix Opcode Index on the host SPI controller 233 // 234 typedef enum { 235 SPI_WREN, // Prefix Opcode 0: Write Enable 236 SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register 237 } PREFIX_OPCODE_INDEX; 238 239 // 240 // Opcode Menu Index on the host SPI controller 241 // 242 typedef enum { 243 SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address 244 SPI_READ, // Opcode 1: READ, Read cycle with address 245 SPI_RDSR, // Opcode 2: Read Status Register, No address 246 SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address 247 SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address 248 SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address 249 SPI_PROG, // Opcode 6: Byte Program, Write cycle with address 250 SPI_WRSR, // Opcode 7: Write Status Register, No address 251 } SPI_OPCODE_INDEX; 252 253 #endif 254
