Home | History | Annotate | Download | only in CodeGen 
      1 //===-- OptimizePHIs.cpp - Optimize machine instruction PHIs --------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This pass optimizes machine instruction PHIs to take advantage of
     11 // opportunities created during DAG legalization.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #define DEBUG_TYPE "phi-opt"
     16 #include "llvm/CodeGen/Passes.h"
     17 #include "llvm/CodeGen/MachineFunctionPass.h"
     18 #include "llvm/CodeGen/MachineInstr.h"
     19 #include "llvm/CodeGen/MachineRegisterInfo.h"
     20 #include "llvm/Target/TargetInstrInfo.h"
     21 #include "llvm/Function.h"
     22 #include "llvm/ADT/SmallPtrSet.h"
     23 #include "llvm/ADT/Statistic.h"
     24 using namespace llvm;
     25 
     26 STATISTIC(NumPHICycles, "Number of PHI cycles replaced");
     27 STATISTIC(NumDeadPHICycles, "Number of dead PHI cycles");
     28 
     29 namespace {
     30   class OptimizePHIs : public MachineFunctionPass {
     31     MachineRegisterInfo *MRI;
     32     const TargetInstrInfo *TII;
     33 
     34   public:
     35     static char ID; // Pass identification
     36     OptimizePHIs() : MachineFunctionPass(ID) {
     37       initializeOptimizePHIsPass(*PassRegistry::getPassRegistry());
     38     }
     39 
     40     virtual bool runOnMachineFunction(MachineFunction &MF);
     41 
     42     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
     43       AU.setPreservesCFG();
     44       MachineFunctionPass::getAnalysisUsage(AU);
     45     }
     46 
     47   private:
     48     typedef SmallPtrSet<MachineInstr*, 16> InstrSet;
     49     typedef SmallPtrSetIterator<MachineInstr*> InstrSetIterator;
     50 
     51     bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg,
     52                                InstrSet &PHIsInCycle);
     53     bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle);
     54     bool OptimizeBB(MachineBasicBlock &MBB);
     55   };
     56 }
     57 
     58 char OptimizePHIs::ID = 0;
     59 INITIALIZE_PASS(OptimizePHIs, "opt-phis",
     60                 "Optimize machine instruction PHIs", false, false)
     61 
     62 FunctionPass *llvm::createOptimizePHIsPass() { return new OptimizePHIs(); }
     63 
     64 bool OptimizePHIs::runOnMachineFunction(MachineFunction &Fn) {
     65   MRI = &Fn.getRegInfo();
     66   TII = Fn.getTarget().getInstrInfo();
     67 
     68   // Find dead PHI cycles and PHI cycles that can be replaced by a single
     69   // value.  InstCombine does these optimizations, but DAG legalization may
     70   // introduce new opportunities, e.g., when i64 values are split up for
     71   // 32-bit targets.
     72   bool Changed = false;
     73   for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
     74     Changed |= OptimizeBB(*I);
     75 
     76   return Changed;
     77 }
     78 
     79 /// IsSingleValuePHICycle - Check if MI is a PHI where all the source operands
     80 /// are copies of SingleValReg, possibly via copies through other PHIs.  If
     81 /// SingleValReg is zero on entry, it is set to the register with the single
     82 /// non-copy value.  PHIsInCycle is a set used to keep track of the PHIs that
     83 /// have been scanned.
     84 bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI,
     85                                          unsigned &SingleValReg,
     86                                          InstrSet &PHIsInCycle) {
     87   assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction");
     88   unsigned DstReg = MI->getOperand(0).getReg();
     89 
     90   // See if we already saw this register.
     91   if (!PHIsInCycle.insert(MI))
     92     return true;
     93 
     94   // Don't scan crazily complex things.
     95   if (PHIsInCycle.size() == 16)
     96     return false;
     97 
     98   // Scan the PHI operands.
     99   for (unsigned i = 1; i != MI->getNumOperands(); i += 2) {
    100     unsigned SrcReg = MI->getOperand(i).getReg();
    101     if (SrcReg == DstReg)
    102       continue;
    103     MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
    104 
    105     // Skip over register-to-register moves.
    106     if (SrcMI && SrcMI->isCopy() &&
    107         !SrcMI->getOperand(0).getSubReg() &&
    108         !SrcMI->getOperand(1).getSubReg() &&
    109         TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
    110       SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
    111     if (!SrcMI)
    112       return false;
    113 
    114     if (SrcMI->isPHI()) {
    115       if (!IsSingleValuePHICycle(SrcMI, SingleValReg, PHIsInCycle))
    116         return false;
    117     } else {
    118       // Fail if there is more than one non-phi/non-move register.
    119       if (SingleValReg != 0)
    120         return false;
    121       SingleValReg = SrcReg;
    122     }
    123   }
    124   return true;
    125 }
    126 
    127 /// IsDeadPHICycle - Check if the register defined by a PHI is only used by
    128 /// other PHIs in a cycle.
    129 bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) {
    130   assert(MI->isPHI() && "IsDeadPHICycle expects a PHI instruction");
    131   unsigned DstReg = MI->getOperand(0).getReg();
    132   assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
    133          "PHI destination is not a virtual register");
    134 
    135   // See if we already saw this register.
    136   if (!PHIsInCycle.insert(MI))
    137     return true;
    138 
    139   // Don't scan crazily complex things.
    140   if (PHIsInCycle.size() == 16)
    141     return false;
    142 
    143   for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg),
    144          E = MRI->use_end(); I != E; ++I) {
    145     MachineInstr *UseMI = &*I;
    146     if (!UseMI->isPHI() || !IsDeadPHICycle(UseMI, PHIsInCycle))
    147       return false;
    148   }
    149 
    150   return true;
    151 }
    152 
    153 /// OptimizeBB - Remove dead PHI cycles and PHI cycles that can be replaced by
    154 /// a single value.
    155 bool OptimizePHIs::OptimizeBB(MachineBasicBlock &MBB) {
    156   bool Changed = false;
    157   for (MachineBasicBlock::iterator
    158          MII = MBB.begin(), E = MBB.end(); MII != E; ) {
    159     MachineInstr *MI = &*MII++;
    160     if (!MI->isPHI())
    161       break;
    162 
    163     // Check for single-value PHI cycles.
    164     unsigned SingleValReg = 0;
    165     InstrSet PHIsInCycle;
    166     if (IsSingleValuePHICycle(MI, SingleValReg, PHIsInCycle) &&
    167         SingleValReg != 0) {
    168       MRI->replaceRegWith(MI->getOperand(0).getReg(), SingleValReg);
    169       MI->eraseFromParent();
    170       ++NumPHICycles;
    171       Changed = true;
    172       continue;
    173     }
    174 
    175     // Check for dead PHI cycles.
    176     PHIsInCycle.clear();
    177     if (IsDeadPHICycle(MI, PHIsInCycle)) {
    178       for (InstrSetIterator PI = PHIsInCycle.begin(), PE = PHIsInCycle.end();
    179            PI != PE; ++PI) {
    180         MachineInstr *PhiMI = *PI;
    181         if (&*MII == PhiMI)
    182           ++MII;
    183         PhiMI->eraseFromParent();
    184       }
    185       ++NumDeadPHICycles;
    186       Changed = true;
    187     }
    188   }
    189   return Changed;
    190 }
    191