1 //===----------------------- AMDGPUFrameLowering.cpp ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //==-----------------------------------------------------------------------===// 9 // 10 // Interface to describe a layout of a stack frame on a AMDGPU target machine. 11 // 12 //===----------------------------------------------------------------------===// 13 #include "AMDGPUFrameLowering.h" 14 #include "AMDGPURegisterInfo.h" 15 #include "AMDGPUSubtarget.h" 16 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/IR/Instructions.h" 20 21 using namespace llvm; 22 AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, unsigned StackAl, 23 int LAO, unsigned TransAl) 24 : TargetFrameLowering(D, StackAl, LAO, TransAl) { } 25 26 AMDGPUFrameLowering::~AMDGPUFrameLowering() { } 27 28 unsigned AMDGPUFrameLowering::getStackWidth(const MachineFunction &MF) const { 29 30 // XXX: Hardcoding to 1 for now. 31 // 32 // I think the StackWidth should stored as metadata associated with the 33 // MachineFunction. This metadata can either be added by a frontend, or 34 // calculated by a R600 specific LLVM IR pass. 35 // 36 // The StackWidth determines how stack objects are laid out in memory. 37 // For a vector stack variable, like: int4 stack[2], the data will be stored 38 // in the following ways depending on the StackWidth. 39 // 40 // StackWidth = 1: 41 // 42 // T0.X = stack[0].x 43 // T1.X = stack[0].y 44 // T2.X = stack[0].z 45 // T3.X = stack[0].w 46 // T4.X = stack[1].x 47 // T5.X = stack[1].y 48 // T6.X = stack[1].z 49 // T7.X = stack[1].w 50 // 51 // StackWidth = 2: 52 // 53 // T0.X = stack[0].x 54 // T0.Y = stack[0].y 55 // T1.X = stack[0].z 56 // T1.Y = stack[0].w 57 // T2.X = stack[1].x 58 // T2.Y = stack[1].y 59 // T3.X = stack[1].z 60 // T3.Y = stack[1].w 61 // 62 // StackWidth = 4: 63 // T0.X = stack[0].x 64 // T0.Y = stack[0].y 65 // T0.Z = stack[0].z 66 // T0.W = stack[0].w 67 // T1.X = stack[1].x 68 // T1.Y = stack[1].y 69 // T1.Z = stack[1].z 70 // T1.W = stack[1].w 71 return 1; 72 } 73 74 /// \returns The number of registers allocated for \p FI. 75 int AMDGPUFrameLowering::getFrameIndexReference(const MachineFunction &MF, 76 int FI, 77 unsigned &FrameReg) const { 78 const MachineFrameInfo *MFI = MF.getFrameInfo(); 79 const AMDGPURegisterInfo *RI 80 = MF.getSubtarget<AMDGPUSubtarget>().getRegisterInfo(); 81 82 // Fill in FrameReg output argument. 83 FrameReg = RI->getFrameRegister(MF); 84 85 // Start the offset at 2 so we don't overwrite work group information. 86 // XXX: We should only do this when the shader actually uses this 87 // information. 88 unsigned OffsetBytes = 2 * (getStackWidth(MF) * 4); 89 int UpperBound = FI == -1 ? MFI->getNumObjects() : FI; 90 91 for (int i = MFI->getObjectIndexBegin(); i < UpperBound; ++i) { 92 OffsetBytes = alignTo(OffsetBytes, MFI->getObjectAlignment(i)); 93 OffsetBytes += MFI->getObjectSize(i); 94 // Each register holds 4 bytes, so we must always align the offset to at 95 // least 4 bytes, so that 2 frame objects won't share the same register. 96 OffsetBytes = alignTo(OffsetBytes, 4); 97 } 98 99 if (FI != -1) 100 OffsetBytes = alignTo(OffsetBytes, MFI->getObjectAlignment(FI)); 101 102 return OffsetBytes / (getStackWidth(MF) * 4); 103 } 104 105
