1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <assert.h> 33 #include <gic_v2.h> 34 #include <interrupt_mgmt.h> 35 #include <mmio.h> 36 37 /******************************************************************************* 38 * GIC Distributor interface accessors for reading entire registers 39 ******************************************************************************/ 40 41 unsigned int gicd_read_igroupr(unsigned int base, unsigned int id) 42 { 43 unsigned n = id >> IGROUPR_SHIFT; 44 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); 45 } 46 47 unsigned int gicd_read_isenabler(unsigned int base, unsigned int id) 48 { 49 unsigned n = id >> ISENABLER_SHIFT; 50 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); 51 } 52 53 unsigned int gicd_read_icenabler(unsigned int base, unsigned int id) 54 { 55 unsigned n = id >> ICENABLER_SHIFT; 56 return mmio_read_32(base + GICD_ICENABLER + (n << 2)); 57 } 58 59 unsigned int gicd_read_ispendr(unsigned int base, unsigned int id) 60 { 61 unsigned n = id >> ISPENDR_SHIFT; 62 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); 63 } 64 65 unsigned int gicd_read_icpendr(unsigned int base, unsigned int id) 66 { 67 unsigned n = id >> ICPENDR_SHIFT; 68 return mmio_read_32(base + GICD_ICPENDR + (n << 2)); 69 } 70 71 unsigned int gicd_read_isactiver(unsigned int base, unsigned int id) 72 { 73 unsigned n = id >> ISACTIVER_SHIFT; 74 return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); 75 } 76 77 unsigned int gicd_read_icactiver(unsigned int base, unsigned int id) 78 { 79 unsigned n = id >> ICACTIVER_SHIFT; 80 return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); 81 } 82 83 unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int id) 84 { 85 unsigned n = id >> IPRIORITYR_SHIFT; 86 return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); 87 } 88 89 unsigned int gicd_read_itargetsr(unsigned int base, unsigned int id) 90 { 91 unsigned n = id >> ITARGETSR_SHIFT; 92 return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); 93 } 94 95 unsigned int gicd_read_icfgr(unsigned int base, unsigned int id) 96 { 97 unsigned n = id >> ICFGR_SHIFT; 98 return mmio_read_32(base + GICD_ICFGR + (n << 2)); 99 } 100 101 unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id) 102 { 103 unsigned n = id >> CPENDSGIR_SHIFT; 104 return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); 105 } 106 107 unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id) 108 { 109 unsigned n = id >> SPENDSGIR_SHIFT; 110 return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); 111 } 112 113 /******************************************************************************* 114 * GIC Distributor interface accessors for writing entire registers 115 ******************************************************************************/ 116 117 void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val) 118 { 119 unsigned n = id >> IGROUPR_SHIFT; 120 mmio_write_32(base + GICD_IGROUPR + (n << 2), val); 121 } 122 123 void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val) 124 { 125 unsigned n = id >> ISENABLER_SHIFT; 126 mmio_write_32(base + GICD_ISENABLER + (n << 2), val); 127 } 128 129 void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val) 130 { 131 unsigned n = id >> ICENABLER_SHIFT; 132 mmio_write_32(base + GICD_ICENABLER + (n << 2), val); 133 } 134 135 void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val) 136 { 137 unsigned n = id >> ISPENDR_SHIFT; 138 mmio_write_32(base + GICD_ISPENDR + (n << 2), val); 139 } 140 141 void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val) 142 { 143 unsigned n = id >> ICPENDR_SHIFT; 144 mmio_write_32(base + GICD_ICPENDR + (n << 2), val); 145 } 146 147 void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val) 148 { 149 unsigned n = id >> ISACTIVER_SHIFT; 150 mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); 151 } 152 153 void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val) 154 { 155 unsigned n = id >> ICACTIVER_SHIFT; 156 mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); 157 } 158 159 void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val) 160 { 161 unsigned n = id >> IPRIORITYR_SHIFT; 162 mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); 163 } 164 165 void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val) 166 { 167 unsigned n = id >> ITARGETSR_SHIFT; 168 mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); 169 } 170 171 void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val) 172 { 173 unsigned n = id >> ICFGR_SHIFT; 174 mmio_write_32(base + GICD_ICFGR + (n << 2), val); 175 } 176 177 void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val) 178 { 179 unsigned n = id >> CPENDSGIR_SHIFT; 180 mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); 181 } 182 183 void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val) 184 { 185 unsigned n = id >> SPENDSGIR_SHIFT; 186 mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); 187 } 188 189 /******************************************************************************* 190 * GIC Distributor interface accessors for individual interrupt manipulation 191 ******************************************************************************/ 192 unsigned int gicd_get_igroupr(unsigned int base, unsigned int id) 193 { 194 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 195 unsigned int reg_val = gicd_read_igroupr(base, id); 196 197 return (reg_val >> bit_num) & 0x1; 198 } 199 200 void gicd_set_igroupr(unsigned int base, unsigned int id) 201 { 202 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 203 unsigned int reg_val = gicd_read_igroupr(base, id); 204 205 gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); 206 } 207 208 void gicd_clr_igroupr(unsigned int base, unsigned int id) 209 { 210 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 211 unsigned int reg_val = gicd_read_igroupr(base, id); 212 213 gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); 214 } 215 216 void gicd_set_isenabler(unsigned int base, unsigned int id) 217 { 218 unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); 219 220 gicd_write_isenabler(base, id, (1 << bit_num)); 221 } 222 223 void gicd_set_icenabler(unsigned int base, unsigned int id) 224 { 225 unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); 226 227 gicd_write_icenabler(base, id, (1 << bit_num)); 228 } 229 230 void gicd_set_ispendr(unsigned int base, unsigned int id) 231 { 232 unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); 233 234 gicd_write_ispendr(base, id, (1 << bit_num)); 235 } 236 237 void gicd_set_icpendr(unsigned int base, unsigned int id) 238 { 239 unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); 240 241 gicd_write_icpendr(base, id, (1 << bit_num)); 242 } 243 244 void gicd_set_isactiver(unsigned int base, unsigned int id) 245 { 246 unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); 247 248 gicd_write_isactiver(base, id, (1 << bit_num)); 249 } 250 251 void gicd_set_icactiver(unsigned int base, unsigned int id) 252 { 253 unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); 254 255 gicd_write_icactiver(base, id, (1 << bit_num)); 256 } 257 258 /* 259 * Make sure that the interrupt's group is set before expecting 260 * this function to do its job correctly. 261 */ 262 void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri) 263 { 264 unsigned int reg = base + GICD_IPRIORITYR + (id & ~3); 265 unsigned int shift = (id & 3) << 3; 266 unsigned int reg_val = mmio_read_32(reg); 267 268 /* 269 * Enforce ARM recommendation to manage priority values such 270 * that group1 interrupts always have a lower priority than 271 * group0 interrupts. 272 * Note, lower numerical values are higher priorities so the comparison 273 * checks below are reversed from what might be expected. 274 */ 275 assert(gicd_get_igroupr(base, id) == GRP1 ? 276 pri >= GIC_HIGHEST_NS_PRIORITY && 277 pri <= GIC_LOWEST_NS_PRIORITY : 278 pri >= GIC_HIGHEST_SEC_PRIORITY && 279 pri <= GIC_LOWEST_SEC_PRIORITY); 280 281 reg_val &= ~(GIC_PRI_MASK << shift); 282 reg_val |= (pri & GIC_PRI_MASK) << shift; 283 mmio_write_32(reg, reg_val); 284 } 285 286 void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int target) 287 { 288 unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); 289 unsigned int reg_val = gicd_read_itargetsr(base, id); 290 291 gicd_write_itargetsr(base, id, reg_val | (target << (byte_off << 3))); 292 } 293 294 /******************************************************************************* 295 * This function allows the interrupt management framework to determine (through 296 * the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to 297 * route it to EL3. The interrupt line is represented as the bit position of the 298 * IRQ or FIQ bit in the SCR_EL3. 299 ******************************************************************************/ 300 uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type) 301 { 302 uint32_t gicc_ctlr; 303 304 /* Non-secure interrupts are signalled on the IRQ line always */ 305 if (type == INTR_TYPE_NS) 306 return __builtin_ctz(SCR_IRQ_BIT); 307 308 /* 309 * Secure interrupts are signalled using the IRQ line if the FIQ_EN 310 * bit is not set else they are signalled using the FIQ line. 311 */ 312 gicc_ctlr = gicc_read_ctlr(cpuif_base); 313 if (gicc_ctlr & FIQ_EN) 314 return __builtin_ctz(SCR_FIQ_BIT); 315 else 316 return __builtin_ctz(SCR_IRQ_BIT); 317 } 318
