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    Searched defs:regValue (Results 1 - 4 of 4) sorted by null

  /external/mesa3d/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_surface.c 119 ADDR_REGISTER_VALUE regValue = {0};
126 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
127 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
128 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
130 regValue.backendDisables = amdinfo->backend_disable[0];
131 regValue.pTileConfig = amdinfo->gb_tile_mode;
132 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
134 regValue.pMacroTileConfig = NULL;
135 regValue.noOfMacroEntries = 0;
137 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode
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  /external/mesa3d/src/gallium/winsys/amdgpu/drm/
amdgpu_surface.c 103 ADDR_REGISTER_VALUE regValue = {0};
110 regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
111 regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
112 regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
114 regValue.backendDisables = ws->amdinfo.backend_disable[0];
115 regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
116 regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
118 regValue.pMacroTileConfig = NULL;
119 regValue.noOfMacroEntries = 0;
121 regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode
    [all...]
  /external/mesa3d/src/amd/addrlib/
addrinterface.h 319 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data
    [all...]
  /device/google/contexthub/firmware/os/drivers/st_lsm6dsm/
st_lsm6dsm.c     [all...]

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