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    Searched defs:reg_size (Results 1 - 21 of 21) sorted by null

  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_ir_vec4.h 79 reg->nr += suboffset / REG_SIZE;
80 reg->offset = suboffset % REG_SIZE;
87 reg->nr += suboffset / REG_SIZE;
88 reg->subnr = suboffset % REG_SIZE;
232 (r.file == UNIFORM ? 16 : REG_SIZE) + r.offset +
252 t1.offset += 4 * REG_SIZE;
389 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + inst->size_written,
390 REG_SIZE);
402 const unsigned reg_size = local
403 inst->src[i].file == UNIFORM || inst->src[i].file == IMM ? 16 : REG_SIZE;
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brw_fs_reg_allocate.cpp 39 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE;
40 reg->offset %= REG_SIZE;
758 const unsigned reg_size = dst.component_size(bld.dispatch_width()) / local
759 REG_SIZE;
760 assert(count % reg_size == 0);
762 for (unsigned i = 0; i < count / reg_size; i++) {
771 spill_offset < (1 << 12) * REG_SIZE);
783 dst.offset += reg_size * REG_SIZE;
784 spill_offset += reg_size * REG_SIZE
792 const unsigned reg_size = src.component_size(bld.dispatch_width()) \/ local
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brw_vec4.cpp 203 return size_written > REG_SIZE;
220 return mlen * REG_SIZE;
224 return mlen * REG_SIZE;
1008 int reg = inst->src[i].nr + inst->src[i].offset / REG_SIZE;
1027 int reg = inst->dst.nr + inst->dst.offset / REG_SIZE;
1541 const unsigned reg_size = (inst->dst.file == UNIFORM ? 16 : REG_SIZE); local
1634 const unsigned reg_size = (inst->src[i].file == UNIFORM ? 16 : REG_SIZE); local
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  /external/v8/src/arm64/
instructions-arm64.cc 75 static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
80 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
82 for (unsigned i = width; i < reg_size; i *= 2) {
93 unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits; local
132 return RepeatBitsAcrossReg(reg_size,
assembler-arm64.h 131 int reg_size; member in struct:v8::internal::CPURegister
143 reg_size = 0;
149 reg_size = r.reg_size;
156 reg_size = r.reg_size;
219 reg_size = 0;
225 reg_size = r.reg_size;
232 reg_size = r.reg_size
1191 int reg_size = rd.SizeInBits(); local
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disasm-arm64.cc 231 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits local
233 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) {
256 bool DisassemblingDecoder::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
257 DCHECK((reg_size == kXRegSizeInBits) ||
258 ((reg_size == kWRegSizeInBits) && (value <= 0xffffffff)));
269 if ((reg_size == kXRegSizeInBits) &&
276 if ((reg_size == kWRegSizeInBits) &&
1510 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits local
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assembler-arm64.cc 2364 unsigned reg_size = rd.SizeInBits(); local
2399 unsigned reg_size = rd.SizeInBits(); local
2490 unsigned reg_size = rd.SizeInBits(); local
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macro-assembler-arm64.cc 68 unsigned reg_size = rd.SizeInBits(); local
123 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
186 unsigned reg_size = rd.SizeInBits(); local
197 if (CountClearHalfWords(~imm, reg_size) >
198 CountClearHalfWords(imm, reg_size)) {
210 DCHECK((reg_size % 16) == 0);
320 unsigned MacroAssembler::CountClearHalfWords(uint64_t imm, unsigned reg_size) {
321 DCHECK((reg_size % 8) == 0);
323 for (unsigned i = 0; i < (reg_size / 16); i++) {
335 bool MacroAssembler::IsImmMovz(uint64_t imm, unsigned reg_size) {
418 int reg_size = dst.SizeInBits(); local
440 int reg_size = dst.SizeInBits(); local
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  /external/vixl/src/aarch64/
instructions-aarch64.cc 51 static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
56 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
58 for (unsigned i = width; i < reg_size; i *= 2) {
128 unsigned reg_size = GetSixtyFourBits() ? kXRegSize : kWRegSize; local
167 return RepeatBitsAcrossReg(reg_size,
debugger-aarch64.cc 650 const uint64_t reg_size = target_reg.GetSizeInBits(); local
652 const uint64_t count = reg_size / format_size;
660 uint64_t data = reg_value >> (reg_size - (i * format_size));
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assembler-aarch64.h 767 unsigned reg_size = rd.GetSizeInBits(); local
768 VIXL_ASSERT(shift < reg_size);
769 ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1);
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disasm-aarch64.cc 264 unsigned reg_size = local
266 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->GetImmLogical())) {
292 bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
293 VIXL_ASSERT((reg_size == kXRegSize) ||
294 ((reg_size == kWRegSize) && (value <= 0xffffffff)));
305 if ((reg_size == kXRegSize) &&
312 if ((reg_size == kWRegSize) && (((value & 0xffff0000) == 0xffff0000) ||
4241 unsigned reg_size = kXRegSize; local
4554 unsigned reg_size = local
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macro-assembler-aarch64.cc 432 unsigned reg_size = rd.GetSizeInBits(); local
443 if (CountClearHalfWords(~imm, reg_size) >
444 CountClearHalfWords(imm, reg_size)) {
460 VIXL_ASSERT((reg_size % 16) == 0);
462 for (unsigned i = 0; i < (reg_size / 16); i++) {
500 int reg_size = dst.GetSizeInBits(); local
502 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) {
509 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) {
516 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) {
773 unsigned reg_size = rd.GetSizeInBits() local
1526 int reg_size = dst.GetSizeInBits(); local
1925 int reg_size = registers.GetRegisterSizeInBytes(); local
1957 int reg_size = registers.GetRegisterSizeInBytes(); local
2256 const int reg_size = registers.GetRegisterSizeInBytes(); local
2307 int reg_size = registers.GetRegisterSizeInBytes(); local
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simulator-aarch64.cc 298 uint64_t Simulator::AddWithCarry(unsigned reg_size,
304 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize));
306 uint64_t max_uint = (reg_size == kWRegSize) ? kWMaxUInt : kXMaxUInt;
307 uint64_t reg_mask = (reg_size == kWRegSize) ? kWRegMask : kXRegMask;
308 uint64_t sign_mask = (reg_size == kWRegSize) ? kWSignMask : kXSignMask;
315 ReadNzcv().SetN(CalcNFlag(result, reg_size));
337 int64_t Simulator::ShiftOperand(unsigned reg_size,
341 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize))
950 int reg_size = GetPrintRegSizeInBytes(format); local
1084 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1124 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1141 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1151 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1171 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1191 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1232 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1244 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1857 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
1940 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
2110 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
2159 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local
2213 unsigned reg_size = (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize; local
3928 int reg_size = RegisterSizeInBytesFromFormat(vf); local
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  /external/jemalloc/src/
stats.c 69 size_t reg_size, run_size, curregs; local
85 CTL_M2_GET("arenas.bin.0.size", j, &reg_size, size_t);
159 reg_size, j, curregs * reg_size, nmalloc,
169 reg_size, j, curregs * reg_size, nmalloc,
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  /external/jemalloc/include/jemalloc/internal/
arena.h 248 * reg_interval has at least the same minimum alignment as reg_size; this
254 size_t reg_size; member in struct:arena_bin_info_s
259 /* Interval between regions (reg_size + (redzone_size << 1)). */
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  /toolchain/binutils/binutils-2.25/include/opcode/
cris.h 92 unsigned int reg_size; member in struct:cris_spec_reg
  /external/mesa3d/src/gallium/drivers/etnaviv/
etnaviv_compiler.c 130 size_t reg_size; member in struct:etna_compile_file
256 for (int idx = 0; idx < file->reg_size; ++idx) {
302 for (int idx = 0; idx < file->reg_size; ++idx)
512 c->file[x].reg_size = c->info.file_max[x] + 1;
514 for (int sub = 0; sub < c->file[x].reg_size; ++sub) {
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  /external/vixl/test/aarch64/
test-assembler-aarch64.cc 8121 int reg_size = sizeof(T) * 8; local
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  /art/compiler/optimizing/
code_generator_arm64.cc 191 int64_t reg_size = kXRegSizeInBytes; local
192 int64_t max_ls_pair_offset = spill_offset + core_spill_size + fp_spill_size - 2 * reg_size;
193 uint32_t ls_access_size = WhichPowerOf2(reg_size);
202 int64_t new_max_ls_pair_offset = fp_spill_size - 2 * reg_size;
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  /toolchain/binutils/binutils-2.25/gas/config/
tc-aarch64.c 4335 int reg_size = ele_size[vectype->type] * vectype->width; local
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