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    Searched defs:rex_ (Results 1 - 3 of 3) sorted by null

  /art/compiler/utils/x86_64/
assembler_x86_64.h 83 return rex_;
101 && (reg.NeedsRex() == ((rex_ & 1) != 0)); // REX.000B bits match.
110 Operand() : rex_(0), length_(0), fixup_(nullptr) { }
115 rex_ |= 0x41; // REX.000B
125 rex_ |= 0x41; // REX.000B
128 rex_ |= 0x42; // REX.00X0
152 uint8_t rex_; member in class:art::x86_64::Operand
157 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); }
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  /external/swiftshader/third_party/subzero/src/
IceTargetLoweringX8664Traits.h 104 uint8_t rexX() const { return (rex_ & RexX) != RexX ? RexNone : RexX; }
105 uint8_t rexB() const { return (rex_ & RexB) != RexB ? RexNone : RexB; }
137 rex_ = (rm & 0x08) ? RexB : RexNone;
145 rex_ =
166 uint8_t rex_ = 0; member in class:Ice::X8664::TargetX8664Traits::Operand
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  /external/v8/src/x64/
disasm-x64.cc 296 rex_(0),
327 byte rex_; member in class:disasm::DisassemblerX64
339 rex_ = rex;
342 bool rex() { return rex_ != 0; }
344 bool rex_b() { return (rex_ & 0x01) != 0; }
347 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); }
349 bool rex_x() { return (rex_ & 0x02) != 0; }
351 bool rex_r() { return (rex_ & 0x04) != 0; }
353 bool rex_w() { return (rex_ & 0x08) != 0; }
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