/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
armVCM4P10_InterpolateLuma_Copy_unsafe_s.s | 48 srcStep RN 1 76 M_LDR x0, [pSrc], srcStep 77 M_LDR x1, [pSrc], srcStep 79 M_LDR x2, [pSrc], srcStep 81 M_LDR x3, [pSrc], srcStep 88 M_LDR x0, [pSrc], srcStep 90 M_LDR x2, [pSrc], srcStep 97 M_LDR x0, [pSrc], srcStep 100 M_LDR x2, [pSrc], srcStep 111 M_LDR x0, [pSrc], srcStep [all...] |
armVCM4P10_InterpolateLuma_Align_unsafe_s.s | 41 srcStep RN 1 92 ADD pSrc, pSrc, srcStep 103 ADD pSrc, pSrc, srcStep 119 ADD pSrc, pSrc, srcStep 135 ADD pSrc, pSrc, srcStep 150 MOV srcStep, #12 192 M_LDR x0, [pSrc], srcStep 203 M_LDR x0, [pSrc], srcStep 216 M_LDR x0, [pSrc], srcStep 229 M_LDR x0, [pSrc], srcStep [all...] |
armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 60 srcStep RN 1 99 M_STR srcStep, pSrcStep 103 LDR ValD, [pSrc, srcStep] ;// Load row 1 [d1 c1 b1 a1] 105 LDR ValH, [pSrc, srcStep] ;// Load [h1 g1 f1 e1] 107 LDRB Temp2, [pSrc, srcStep] ;// Load row 1 [l1 k1 j1 i1] 178 M_LDR srcStep, pSrcStep 183 ADD pSrc, pSrc, srcStep, LSL #1 188 SUB pSrc, pSrc, srcStep, LSL #2
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omxVCM4P10_InterpolateLuma_s.s | 35 ;// [in] srcStep Reference frame step in byte 52 ;// srcStep or dstStep >= roi.width. 58 ;// srcStep and dstStep is multiple of 8. 92 srcStep RN 1 162 STM pArgs, {pSrc,srcStep,pDst,dstStep} 225 SUB pSrc, pSrc, srcStep, LSL #1 243 LDM pArgs, {pSrc, srcStep, pDst, dstStep} 244 SUB pSrc, pSrc, srcStep, LSL #1 250 MOV srcStep, #4 260 SUB pSrc, pSrc, srcStep, LSL # [all...] |
armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 71 srcStep RN 1 122 M_STR srcStep, pSrcStep 127 LDR ValD, [pSrc, srcStep] ;// Load row 1 [d1 c1 b1 a1] 129 LDR ValH, [pSrc, srcStep] ;// Load [h1 g1 f1 e1] 131 LDRB Temp2, [pSrc, srcStep] ;// Load row 1 [l1 k1 j1 i1] 184 M_LDR srcStep, pSrcStep 219 ADD pSrc, pSrc, srcStep, LSL #1 232 MOV srcStep, #16 242 M_LDR ValCA, [pSrc], srcStep ;// Load [0 c 0 a] 243 M_LDR ValDB, [pSrc], srcStep ;// Load [0 d 0 b [all...] |
armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 68 srcStep RN 1 147 M_LDR ValC, [pSrc], srcStep ;// Load [c3 c2 c1 c0] 148 M_LDR ValD, [pSrc], srcStep ;// Load [d3 d2 d1 d0] 149 M_LDR ValE, [pSrc], srcStep ;// Load [e3 e2 e1 e0] 150 SUB pSrc, pSrc, srcStep, LSL #2 161 LDR ValD, [pSrc, srcStep, LSL #1] ;// Load [d3 d2 d1 d0] 167 LDR ValF, [pSrc, srcStep, LSL #2] ;// Load [f3 f2 f1 f0] 168 M_LDR ValB, [pSrc], srcStep ;// Load [b3 b2 b1 b0] 175 SUB ValA, pSrc, srcStep, LSL #1 186 LDR ValG, [pSrc, srcStep, LSL #2] ;// Load [g3 g2 g1 g0 [all...] |
armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 61 srcStep RN 1 118 M_LDR ValC, [pSrc], srcStep ;// Load [c3 c2 c1 c0] 119 M_LDR ValD, [pSrc], srcStep ;// Load [d3 d2 d1 d0] 120 M_LDR ValE, [pSrc], srcStep ;// Load [e3 e2 e1 e0] 121 SUB pSrc, pSrc, srcStep, LSL #2 133 LDR ValD, [pSrc, srcStep, LSL #1] ;// Load [d3 d2 d1 d0] 140 LDR ValF, [pSrc, srcStep, LSL #2] ;// Load [f3 f2 f1 f0] 141 M_LDR ValB, [pSrc], srcStep ;// Load [b3 b2 b1 b0] 148 SUB ValA, pSrc, srcStep, LSL #1 161 LDR ValG, [pSrc, srcStep, LSL #2] ;// Load [g3 g2 g1 g0 [all...] |
/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
armVCM4P10_InterpolateLuma_Copy_unsafe_s.s | 48 srcStep RN 1 76 M_LDR x0, [pSrc], srcStep 77 M_LDR x1, [pSrc], srcStep 79 M_LDR x2, [pSrc], srcStep 81 M_LDR x3, [pSrc], srcStep 88 M_LDR x0, [pSrc], srcStep 90 M_LDR x2, [pSrc], srcStep 97 M_LDR x0, [pSrc], srcStep 100 M_LDR x2, [pSrc], srcStep 111 M_LDR x0, [pSrc], srcStep [all...] |
armVCM4P10_InterpolateLuma_Align_unsafe_s.s | 41 srcStep RN 1 92 ADD pSrc, pSrc, srcStep 103 ADD pSrc, pSrc, srcStep 119 ADD pSrc, pSrc, srcStep 135 ADD pSrc, pSrc, srcStep 150 MOV srcStep, #12 192 M_LDR x0, [pSrc], srcStep 203 M_LDR x0, [pSrc], srcStep 216 M_LDR x0, [pSrc], srcStep 229 M_LDR x0, [pSrc], srcStep [all...] |
armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 40 srcStep RN 1 87 VLD1 dSrc0, [pSrc], srcStep ;// [a0 a1 a2 a3 .. ] 88 ADD Temp, pSrc, srcStep, LSL #2 89 VLD1 dSrc1, [pSrc], srcStep ;// [b0 b1 b2 b3 .. ] 91 VLD1 dSrc5, [Temp], srcStep 93 VLD1 dSrc2, [pSrc], srcStep ;// [c0 c1 c2 c3 .. ] 95 VLD1 dSrc3, [pSrc], srcStep 97 VLD1 dSrc6, [Temp], srcStep ;// TeRi 99 VLD1 dSrc4, [pSrc], srcStep 100 VLD1 dSrc7, [Temp], srcStep ;// TeR [all...] |
armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 40 srcStep RN 1 111 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..] 124 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..] 138 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..] 155 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..] 172 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..] 189 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..] 206 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..] 223 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..] 240 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 .. [all...] |
armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 42 srcStep RN 1 103 VLD1 qSrcA01, [pSrc], srcStep ;// Load A register [a0 a1 a2 a3 ..] 107 ; VLD1 qSrcB01, [pSrc], srcStep ;// Load B register [a0 a1 a2 a3 ..] 115 VLD1 qSrcB01, [pSrc], srcStep ;// Load B register [a0 a1 a2 a3 ..] 116 ; VLD1 qSrcC01, [pSrc], srcStep ;// Load C register [a0 a1 a2 a3 ..] 133 VLD1 qSrcC01, [pSrc], srcStep ;// Load C register [a0 a1 a2 a3 ..] 134 ; VLD1 qSrcD01, [pSrc], srcStep ;// Load D register [a0 a1 a2 a3 ..] 152 VLD1 qSrcD01, [pSrc], srcStep ;// Load D register [a0 a1 a2 a3 ..]
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armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 39 srcStep RN 1 133 VLD1 qSrcA01, [pSrc], srcStep ;// [a0 a1 a2 a3 .. a15] 134 ADD r12, pSrc, srcStep, LSL #2 137 VLD1 qSrcF1011, [r12], srcStep 138 VLD1 qSrcB23, [pSrc], srcStep ;// [b0 b1 b2 b3 .. b15] 140 VLD1 qSrcG1213, [r12], srcStep 142 VLD1 qSrcC45, [pSrc], srcStep ;// [c0 c1 c2 c3 .. c15] 144 VLD1 qSrcD67, [pSrc], srcStep 146 VLD1 qSrcE89, [pSrc], srcStep 151 VLD1 qSrcH1415, [r12], srcStep [all...] |
omxVCM4P10_InterpolateLuma_s.s | 35 ;// [in] srcStep Reference frame step in byte 52 ;// srcStep or dstStep >= roi.width. 58 ;// srcStep and dstStep is multiple of 8. 82 srcStep RN 1 206 STM pArgs, {pSrc,srcStep,pDst,dstStep} 233 ADD Temp, pSrc, srcStep, LSL #1 234 VLD1 dSrc0, [pSrc], srcStep 235 VLD1 dSrc2, [Temp], srcStep 297 SUB pSrc, pSrc, srcStep, LSL #1 315 SUB pSrc, pSrc, srcStep, LSL # [all...] |
omxVCM4P10_PredictIntra_4x4_s.s | 73 srcStep RN 10 193 ADD srcStep, leftStep, leftStep 195 VLD1 {dLeftVal0[]},[pSrcLeft],srcStep ;// pSrcLeft[0*leftStep] 196 VLD1 {dLeftVal1[]},[pSrcTmp],srcStep ;// pSrcLeft[1*leftStep] 233 ADD srcStep, leftStep, leftStep 235 VLD1 {dLeftVal[0]},[pSrcLeft],srcStep ;// pSrcLeft[0*leftStep] 236 VLD1 {dLeftVal[1]},[pSrcTmp],srcStep ;// pSrcLeft[1*leftStep] 347 ADD srcStep, leftStep, leftStep 350 VLD1 {dLeft[6]},[pSrcLeft],srcStep ;// pSrcLeft[0*leftStep] 351 VLD1 {dLeft[5]},[pSrcTmp],srcStep ;// pSrcLeft[1*leftStep [all...] |
/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
omxVCM4P2_MCReconBlock_s.s | 86 ;// M_LOAD_X $pSrc, $srcStep, $out0, $out1, $scratch, $offset 91 ;// $srcStep The stride on source 106 M_LOAD_X $pSrc, $srcStep, $out0, $out1, $scratch, $offset 109 ADD $pSrc, $pSrc, $srcStep 112 ADD $pSrc, $pSrc, $srcStep 129 ;// M_LOAD_XINT $pSrc, $srcStep, $offset, $word0, $word1, $word2, $word3 135 ;// $srcStep The stride on source 141 ;// $pSrc Incremented by $srcStep 169 M_LOAD_XINT $pSrc, $srcStep, $offset, $word0, $word1, $word2, $word3 175 ADD $pSrc, $pSrc, $srcStep [all...] |
/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
omxVCM4P2_MCReconBlock_s.s | 64 VLD1 dRow0, [pSrc], srcStep 65 VLD1 dRow1, [pSrc], srcStep 66 VLD1 dRow2, [pSrc], srcStep 67 VLD1 dRow3, [pSrc], srcStep 68 VLD1 dRow4, [pSrc], srcStep 69 VLD1 dRow5, [pSrc], srcStep 70 VLD1 dRow6, [pSrc], srcStep 71 VLD1 dRow7, [pSrc], srcStep 111 VLD1 {dRow0, dRow0Shft}, [pSrc], srcStep 113 VLD1 {dRow1, dRow1Shft}, [pSrc], srcStep [all...] |