| /external/vixl/src/aarch64/ |
| decoder-aarch64.cc | 35 void Decoder::DecodeInstruction(const Instruction* instr) {
36 if (instr->ExtractBits(28, 27) == 0) {
37 VisitUnallocated(instr);
39 switch (instr->ExtractBits(27, 24)) {
42 DecodePCRelAddressing(instr);
47 DecodeAddSubImmediate(instr);
62 DecodeDataProcessing(instr);
68 DecodeLogical(instr);
74 DecodeBitfieldExtract(instr);
89 DecodeBranchSystemException(instr);
[all...] |
| disasm-aarch64.h | 49 virtual void Visit##A(const Instruction* instr) VIXL_OVERRIDE;
54 virtual void ProcessOutput(const Instruction* instr);
62 virtual void AppendRegisterNameToOutput(const Instruction* instr,
67 virtual void AppendPCRelativeOffsetToOutput(const Instruction* instr,
72 virtual void AppendCodeRelativeAddressToOutput(const Instruction* instr,
80 virtual void AppendCodeRelativeCodeAddressToOutput(const Instruction* instr,
86 virtual void AppendCodeRelativeDataAddressToOutput(const Instruction* instr,
91 virtual void AppendAddressToOutput(const Instruction* instr,
93 virtual void AppendCodeAddressToOutput(const Instruction* instr,
95 virtual void AppendDataAddressToOutput(const Instruction* instr,
[all...] |
| instrument-aarch64.cc | 254 void Instrument::VisitPCRelAddressing(const Instruction* instr) {
255 USE(instr);
262 void Instrument::VisitAddSubImmediate(const Instruction* instr) {
263 USE(instr);
270 void Instrument::VisitLogicalImmediate(const Instruction* instr) {
271 USE(instr);
278 void Instrument::VisitMoveWideImmediate(const Instruction* instr) {
282 if (instr->IsMovn() && (instr->GetRd() == kZeroRegCode)) {
283 unsigned imm = instr->GetImmMoveWide()
[all...] |
| /external/v8/src/arm64/ |
| decoder-arm64-inl.h | 19 void Decoder<V>::Decode(Instruction *instr) {
20 if (instr->Bits(28, 27) == 0) {
21 V::VisitUnallocated(instr);
23 switch (instr->Bits(27, 24)) {
25 case 0x0: DecodePCRelAddressing(instr); break;
28 case 0x1: DecodeAddSubImmediate(instr); break;
41 case 0xB: DecodeDataProcessing(instr); break;
45 case 0x2: DecodeLogical(instr); break;
49 case 0x3: DecodeBitfieldExtract(instr); break;
62 case 0x7: DecodeBranchSystemException(instr); break
[all...] |
| disasm-arm64.h | 25 #define DECLARE(A) void Visit##A(Instruction* instr);
30 virtual void ProcessOutput(Instruction* instr);
32 void Format(Instruction* instr, const char* mnemonic, const char* format);
33 void Substitute(Instruction* instr, const char* string);
34 int SubstituteField(Instruction* instr, const char* format);
35 int SubstituteRegisterField(Instruction* instr, const char* format);
36 int SubstituteImmediateField(Instruction* instr, const char* format);
37 int SubstituteLiteralField(Instruction* instr, const char* format);
38 int SubstituteBitfieldImmediateField(Instruction* instr, const char* format);
39 int SubstituteShiftField(Instruction* instr, const char* format)
[all...] |
| /external/jacoco/org.jacoco.core/src/org/jacoco/core/instr/ |
| package-info.java | 16 * is the class {@link org.jacoco.core.instr.Instrumenter}.
19 package org.jacoco.core.instr
|
| /platform_testing/libraries/app-helpers/handheld/src/android/platform/test/helpers/handheld/ |
| AbstractQuickSearchBoxHelper.java | 22 public AbstractQuickSearchBoxHelper(Instrumentation instr) {
23 super(instr);
|
| /external/mesa3d/src/compiler/nir/ |
| nir_lower_samplers.c | 39 calc_sampler_offsets(nir_deref *tail, nir_tex_instr *instr,
52 calc_sampler_offsets(tail->child, instr, array_elements,
54 instr->texture_index += deref_array->base_offset * *array_elements;
61 nir_instr_rewrite_src(&instr->instr, &deref_array->indirect,
78 calc_sampler_offsets(tail->child, instr, array_elements,
90 lower_sampler(nir_tex_instr *instr, const struct gl_shader_program *shader_program,
93 if (instr->texture == NULL)
97 assert(instr->sampler == NULL);
99 instr->texture_index = 0
[all...] |
| nir_opt_undef.c | 39 opt_undef_csel(nir_alu_instr *instr)
41 if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel)
44 assert(instr->dest.dest.is_ssa);
47 if (!instr->src[i].src.is_ssa)
50 nir_instr *parent = instr->src[i].src.ssa->parent_instr;
57 nir_instr_rewrite_src(&instr->instr, &instr->src[0].src,
58 instr->src[i == 1 ? 2 : 1].src)
[all...] |
| nir_lower_atomics.c | 39 lower_instr(nir_intrinsic_instr *instr,
44 switch (instr->intrinsic) {
93 if (instr->variables[0]->var->data.mode != nir_var_uniform &&
94 instr->variables[0]->var->data.mode != nir_var_shader_storage &&
95 instr->variables[0]->var->data.mode != nir_var_shared)
98 void *mem_ctx = ralloc_parent(instr);
99 unsigned uniform_loc = instr->variables[0]->var->data.location;
107 offset_const->value.u32[0] = instr->variables[0]->var->data.offset;
109 nir_instr_insert_before(&instr->instr, &offset_const->instr)
[all...] |
| nir_lower_alu_to_scalar.c | 34 nir_alu_ssa_dest_init(nir_alu_instr *instr, unsigned num_components,
37 nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
39 instr->dest.write_mask = (1 << num_components) - 1;
43 lower_reduction(nir_alu_instr *instr, nir_op chan_op, nir_op merge_op,
46 unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
51 nir_alu_ssa_dest_init(chan, 1, instr->dest.dest.ssa.bit_size);
52 nir_alu_src_copy(&chan->src[0], &instr->src[0], chan);
56 nir_alu_src_copy(&chan->src[1], &instr->src[1], chan)
[all...] |
| nir_opt_dce.c | 34 nir_instr *instr; member in struct:__anon27471
38 worklist_push(struct exec_list *worklist, nir_instr *instr)
41 elem->instr = instr;
42 instr->pass_flags = 1;
51 return elem->instr;
67 init_instr(nir_instr *instr, struct exec_list *worklist)
77 instr->pass_flags = 0;
79 switch (instr->type) {
82 worklist_push(worklist, instr);
142 nir_instr *instr = worklist_pop(worklist); local
[all...] |
| nir_search_helpers.h | 39 is_pos_power_of_two(nir_alu_instr *instr, unsigned src, unsigned num_components,
42 nir_const_value *val = nir_src_as_const_value(instr->src[src].src);
49 switch (nir_op_infos[instr->op].input_types[src]) {
69 is_neg_power_of_two(nir_alu_instr *instr, unsigned src, unsigned num_components,
72 nir_const_value *val = nir_src_as_const_value(instr->src[src].src);
79 switch (nir_op_infos[instr->op].input_types[src]) {
95 is_zero_to_one(nir_alu_instr *instr, unsigned src, unsigned num_components,
98 nir_const_value *val = nir_src_as_const_value(instr->src[src].src);
104 switch (nir_op_infos[instr->op].input_types[src]) {
118 is_used_more_than_once(nir_alu_instr *instr)
[all...] |
| nir_opt_constant_folding.c | 42 constant_fold_alu_instr(nir_alu_instr *instr, void *mem_ctx)
46 if (!instr->dest.dest.is_ssa)
59 if (!nir_alu_type_get_type_size(nir_op_infos[instr->op].output_type))
60 bit_size = instr->dest.dest.ssa.bit_size;
62 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
63 if (!instr->src[i].src.is_ssa)
67 !nir_alu_type_get_type_size(nir_op_infos[instr->op].input_sizes[i])) {
68 bit_size = instr->src[i].src.ssa->bit_size;
71 nir_instr *src_instr = instr->src[i].src.ssa->parent_instr;
77 for (unsigned j = 0; j < nir_ssa_alu_instr_src_components(instr, i)
[all...] |
| nir_opt_gcm.c | 51 /* Flags used in the instr->pass_flags field for various instruction states */
61 nir_instr *instr; member in struct:gcm_state
104 * This function also serves to initialize the instr->pass_flags field.
111 nir_foreach_instr_safe(instr, block) {
112 switch (instr->type) {
114 switch (nir_instr_as_alu(instr)->op) {
122 instr->pass_flags = GCM_INSTR_PINNED;
126 instr->pass_flags = 0;
132 switch (nir_instr_as_tex(instr)->op) {
137 instr->pass_flags = GCM_INSTR_PINNED
207 nir_instr *instr = state->instr; local
494 nir_instr *instr = exec_node_data(nir_instr, local
[all...] |
| /external/vixl/src/aarch32/ |
| disasm-aarch32.cc | 52 T32CodeAddressIncrementer(uint32_t instr, uint32_t* code_address)
54 increment_(Disassembler::Is16BitEncoding(instr) ? 2 : 4) {}
[all...] |
| /external/jacoco/org.jacoco.core/src/org/jacoco/core/internal/instr/ |
| IProbeInserter.java | 12 package org.jacoco.core.internal.instr;
|
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Disassembler.h | 33 int arm64_disassemble(uint32_t code, char* instr);
|
| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| ir3_group.c | 38 * (where we have a simple instr[] array), and fanin nodes (where we have
39 * an extra indirection via reg->instr).
43 void (*insert_mov)(void *arr, int idx, struct ir3_instruction *instr);
50 static void arr_insert_mov_out(void *arr, int idx, struct ir3_instruction *instr)
53 ir3_MOV(instr->block, instr, TYPE_F32);
55 static void arr_insert_mov_in(void *arr, int idx, struct ir3_instruction *instr)
58 * instruction already has a pointer to 'instr'. So we cheat a bit and
64 debug_assert(instr->regs_count == 1);
66 in = ir3_instr_create(instr->block, OPC_META_INPUT)
126 struct ir3_instruction *instr = ops->get(arr, i); local
160 struct ir3_instruction *instr = ops->get(arr, i); local
207 struct ir3_instruction *instr = input[i]; local
252 struct ir3_instruction *instr = ir->outputs[i]; local
258 struct ir3_instruction *instr = ir->keeps[i]; local
[all...] |
| ir3_depth.c | 40 * depth(instr) {
43 * foreach (src in instr->regs[1..n])
44 * d = max(d, delayslots(src->instr, n) + depth(src->instr));
87 ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list)
90 list_delinit(&instr->node);
94 if (pos->depth > instr->depth) {
95 list_add(&instr->node, &pos->node);
100 list_addtail(&instr->node, list);
104 ir3_instr_depth(struct ir3_instruction *instr)
180 struct ir3_instruction *instr = ir->indirects[i]; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_gs_nir.cpp | 34 vec4_gs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
38 switch (instr->intrinsic) {
50 vec4_visitor::nir_setup_system_value_intrinsic(instr);
56 vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
61 switch (instr->intrinsic) {
66 nir_const_value *vertex = nir_src_as_const_value(instr->src[0]);
67 nir_const_value *offset_reg = nir_src_as_const_value(instr->src[1]);
69 if (nir_dest_bit_size(instr->dest) == 64) {
71 instr->const_index[0] + offset_reg->u32[0],
78 src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr) / 2)
[all...] |
| /external/v8/src/crankshaft/ |
| hydrogen-canonicalize.cc | 21 HInstruction* instr = it.Current(); local
22 if (instr->IsArithmeticBinaryOperation()) {
23 if (instr->representation().IsInteger32()) {
24 if (instr->HasAtLeastOneUseWithFlagAndNoneWithout(
26 instr->SetFlag(HInstruction::kAllUsesTruncatingToInt32);
28 } else if (instr->representation().IsSmi()) {
29 if (instr->HasAtLeastOneUseWithFlagAndNoneWithout(
31 instr->SetFlag(HInstruction::kAllUsesTruncatingToSmi);
32 } else if (instr->HasAtLeastOneUseWithFlagAndNoneWithout(
35 instr->SetFlag(HInstruction::kAllUsesTruncatingToInt32)
51 HInstruction* instr = it.Current(); local
[all...] |
| /external/v8/src/compiler/ |
| instruction-scheduler.h | 37 void AddInstruction(Instruction* instr);
46 ScheduleGraphNode(Zone* zone, Instruction* instr);
152 int GetInstructionFlags(const Instruction* instr) const;
153 int GetTargetInstructionFlags(const Instruction* instr) const;
156 bool IsBlockTerminator(const Instruction* instr) const;
160 bool HasSideEffect(const Instruction* instr) const {
161 return (GetInstructionFlags(instr) & kHasSideEffect) != 0;
165 bool IsLoadOperation(const Instruction* instr) const {
166 return (GetInstructionFlags(instr) & kIsLoadOperation) != 0;
171 bool MayNeedDeoptCheck(const Instruction* instr) const
[all...] |
| /external/v8/src/compiler/mips/ |
| instruction-scheduler-mips.cc | 15 const Instruction* instr) const {
20 int InstructionScheduler::GetInstructionLatency(const Instruction* instr) {
|
| /external/v8/src/compiler/mips64/ |
| instruction-scheduler-mips64.cc | 15 const Instruction* instr) const {
20 int InstructionScheduler::GetInstructionLatency(const Instruction* instr) {
|
