| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
| metadsp21.d | [all...] |
| metadsp21.s | [all...] |
| metafpu21.d | 591 .*: 2c003321 F ANDS FX\.0,D0Re0,A0FrP
594 .*: 2c01e121 F ANDS FX\.0,D0\.7,RD
597 .*: 2c081f21 F ANDS FX\.1,D0Re0,D1\.7
600 .*: 2c09d121 F ANDS FX\.1,D0\.7,D1Re0
603 .*: 2c100f20 F ANDS FX\.2,D0Re0,D0\.7
606 .*: 2c11c721 F ANDS FX\.2,D0\.7,A1\.3
609 .*: 2c180321 F ANDS FX\.3,D0Re0,A1LbP
612 .*: 2c19c120 F ANDS FX\.3,D0\.7,D0Re0
615 .*: 2c19f521 F ANDS FX\.3,D0\.7,A0\.2
618 .*: 2c203321 F ANDS FX\.4,D0Re0,A0Fr
[all...] |
| metafpu21.s | 583 F ANDS FX.0,D0Re0,A0FrP
586 F ANDS FX.0,D0.7,RD
589 F ANDS FX.1,D0Re0,D1.7
592 F ANDS FX.1,D0.7,D1Re0
595 F ANDS FX.2,D0Re0,D0.7
598 F ANDS FX.2,D0.7,A1.3
601 F ANDS FX.3,D0Re0,A1LbP
604 F ANDS FX.3,D0.7,D0Re0
607 F ANDS FX.3,D0.7,A0.2
610 F ANDS FX.4,D0Re0,A0Fr
[all...] |
| metacore12.s | [all...] |
| metacore12.d | [all...] |
| metacore21.d | [all...] |
| metacore21.s | [all...] |
| /external/v8/src/arm64/ |
| constants-arm64.h | 503 ANDS = 0x60000000,
504 BICS = ANDS | NOT
518 ANDS_w_imm = LogicalImmediateFixed | ANDS,
519 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
545 ANDS_w = LogicalShiftedFixed | ANDS,
546 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
[all...] |
| instructions-arm64.h | 250 // Of the logical (immediate) instructions, only ANDS (and its aliases)
254 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
|
| macro-assembler-arm64-inl.h | 55 void MacroAssembler::Ands(const Register& rd,
60 LogicalMacro(rd, rn, operand, ANDS);
67 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS);
[all...] |
| assembler-arm64.cc | 1194 void Assembler::ands(const Register& rd, function in class:v8::internal::Assembler
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/ |
| anames.go | 20 "ANDS",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/ |
| anames.go | 20 "ANDS",
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| div.asm | 92 ANDS r2, r1, #0x80000000
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_DecodeCoeffsToPair_s.s | 152 ANDS TrailingOnes, Symbol, #3
|
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 188 ANDS Temp3, Counter, #1
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_DecodeCoeffsToPair_s.s | 152 ANDS TrailingOnes, Symbol, #3
|
| /external/vixl/src/aarch64/ |
| constants-aarch64.h | 539 ANDS = 0x60000000,
540 BICS = ANDS | NOT
554 ANDS_w_imm = LogicalImmediateFixed | ANDS,
555 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
581 ANDS_w = LogicalShiftedFixed | ANDS,
582 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
[all...] |
| instructions-aarch64.h | 346 // Of the logical (immediate) instructions, only ANDS (and its aliases)
350 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
|
| macro-assembler-aarch64.cc | 698 void MacroAssembler::Ands(const Register& rd,
702 LogicalMacro(rd, rn, operand, ANDS);
708 Ands(AppropriateZeroRegFor(rn), rn, operand);
802 case ANDS:
821 case ANDS:
[all...] |
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_inline.h | 217 ANDS x7, mask, x7, rrx;
401 "ands %1, %4, %1,rrx\n\t"
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_DecodeCoeffsToPair_s.S | 90 ANDS r1,r7,#3
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 60 ANDS,
|
| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_T2_32.c | 100 #define ANDS 0x4000
757 return push_inst16(compiler, ANDS | RD3(dst) | RN3(arg2));
[all...] |
