| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 67 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS);
204 Adds(AppropriateZeroRegFor(rn), rn, operand);
210 Subs(AppropriateZeroRegFor(rn), rn, operand);
221 Sub(rd, AppropriateZeroRegFor(rd), operand);
229 Subs(rd, AppropriateZeroRegFor(rd), operand);
273 Register zr = AppropriateZeroRegFor(rd);
282 Register zr = AppropriateZeroRegFor(rd);
[all...] |
| assembler-arm64.cc | [all...] |
| assembler-arm64-inl.h | 1194 const Register& Assembler::AppropriateZeroRegFor(const CPURegister& reg) const {
[all...] |
| assembler-arm64.h | [all...] |
| macro-assembler-arm64.cc | 389 Register zr = AppropriateZeroRegFor(rn);
431 LogicalImmediate(dst, AppropriateZeroRegFor(dst), n, imm_s, imm_r, ORR);
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | 521 AppropriateZeroRegFor(dst),
708 Ands(AppropriateZeroRegFor(rn), rn, operand);
[all...] |
| assembler-aarch64.cc | 415 Register zr = AppropriateZeroRegFor(rn);
435 Register zr = AppropriateZeroRegFor(rn);
441 Register zr = AppropriateZeroRegFor(rd);
447 Register zr = AppropriateZeroRegFor(rd);
481 Register zr = AppropriateZeroRegFor(rd);
487 Register zr = AppropriateZeroRegFor(rd);
508 ands(AppropriateZeroRegFor(rn), rn, operand);
670 Register zr = AppropriateZeroRegFor(rd);
677 Register zr = AppropriateZeroRegFor(rd);
804 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MADD)
[all...] |
| assembler-aarch64.h | [all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm64.cc | [all...] |
