| /art/compiler/optimizing/ |
| intrinsics_x86_64.cc | 94 CpuRegister src_curr_addr = locations->GetTemp(0).AsRegister<CpuRegister>();
95 CpuRegister dst_curr_addr = locations->GetTemp(1).AsRegister<CpuRegister>();
96 CpuRegister src_stop_addr = locations->GetTemp(2).AsRegister<CpuRegister>();
149 __ movd(output.AsRegister<CpuRegister>(), input.AsFpuRegister<XmmRegister>(), is64bit);
155 __ movd(output.AsFpuRegister<XmmRegister>(), input.AsRegister<CpuRegister>(), is64bit);
197 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
303 CpuRegister out = output.AsRegister<CpuRegister>();
304 CpuRegister mask = locations->GetTemp(0).AsRegister<CpuRegister>();
484 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
485 CpuRegister op2 = op2_loc.AsRegister<CpuRegister>()
[all...] |
| code_generator_x86_64.cc | 197 Address array_len(array_loc.AsRegister<CpuRegister>(), len_offset);
204 __ movl(length_loc.AsRegister<CpuRegister>(), array_len);
206 __ shrl(length_loc.AsRegister<CpuRegister>(), Immediate(1));
277 locations->Out().AsRegister<CpuRegister>());
324 locations->Out().AsRegister<CpuRegister>());
484 CpuRegister ref_cpu_reg = ref_.AsRegister<CpuRegister>();
485 Register ref_reg = ref_cpu_reg.AsRegister();
577 CpuRegister ref_cpu_reg = ref_.AsRegister<CpuRegister>();
578 Register ref_reg = ref_cpu_reg.AsRegister();
650 bool base_equals_value = (base.AsRegister() == value.AsRegister())
[all...] |
| intrinsics_x86.cc | 102 Register src = locations->InAt(0).AsRegister<Register>();
104 Register dest = locations->InAt(2).AsRegister<Register>();
108 Register temp1 = temp1_loc.AsRegister<Register>();
109 Register temp2 = locations->GetTemp(1).AsRegister<Register>();
110 Register temp3 = locations->GetTemp(2).AsRegister<Register>();
133 __ leal(temp2, Address(src_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0));
156 __ leal(temp3, Address(dest_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0));
211 __ movd(output.AsRegister<Register>(), input.AsFpuRegister<XmmRegister>());
227 __ movd(output.AsFpuRegister<XmmRegister>(), input.AsRegister<Register>());
286 Register out = locations->Out().AsRegister<Register>()
[all...] |
| intrinsics_mips64.cc | 60 GpuRegister trg_reg = trg.AsRegister<GpuRegister>();
152 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
188 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
227 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
228 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
279 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
280 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
314 __ Dsbh(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>());
315 __ Dshd(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>())
[all...] |
| code_generator_x86.cc | 146 Address array_len(array_loc.AsRegister<Register>(), len_offset);
153 __ movl(length_loc.AsRegister<Register>(), array_len);
155 __ shrl(length_loc.AsRegister<Register>(), Immediate(1));
240 Register method_address = locations->InAt(0).AsRegister<Register>();
242 locations->Out().AsRegister<Register>());
296 Register method_address = locations->InAt(0).AsRegister<Register>();
298 locations->Out().AsRegister<Register>());
471 Register ref_reg = ref_.AsRegister<Register>();
558 Register ref_reg = ref_.AsRegister<Register>();
723 Register reg_out = out_.AsRegister<Register>()
[all...] |
| code_generator_mips64.cc | 192 GpuRegister temp = locations->GetTemp(0).AsRegister<GpuRegister>();
196 entry_address = temp_is_a0 ? out.AsRegister<GpuRegister>() : temp;
246 __ StoreToOffset(kStoreWord, out.AsRegister<GpuRegister>(), TMP, /* placeholder */ 0x5678);
282 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
292 GpuRegister temp = locations->GetTemp(0).AsRegister<GpuRegister>();
564 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>();
604 DCHECK_EQ(entrypoint_.AsRegister<GpuRegister>(), T9);
605 __ Jalr(entrypoint_.AsRegister<GpuRegister>());
659 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>();
726 GpuRegister offset = field_offset_.AsRegister<GpuRegister>()
[all...] |
| intrinsics_mips.cc | 72 Register trg_reg = trg.AsRegister<Register>();
171 Register out = locations->Out().AsRegister<Register>();
213 Register in = locations->InAt(0).AsRegister<Register>();
259 Register in = locations->InAt(0).AsRegister<Register>();
260 Register out = locations->Out().AsRegister<Register>();
273 Register in = locations->InAt(0).AsRegister<Register>();
274 Register out = locations->Out().AsRegister<Register>();
447 Register out = locations->Out().AsRegister<Register>();
463 Register in = locations->InAt(0).AsRegister<Register>();
495 Register out = locations->Out().AsRegister<Register>()
[all...] |
| code_generator_mips.cc | 236 Register temp = locations->GetTemp(0).AsRegister<Register>();
240 entry_address = temp_is_a0 ? out.AsRegister<Register>() : temp;
288 Register base = isR6 ? ZERO : locations->InAt(0).AsRegister<Register>();
295 __ StoreToOffset(kStoreWord, out.AsRegister<Register>(), TMP, /* placeholder */ 0x5678);
332 Register out = locations->Out().AsRegister<Register>();
342 Register temp = locations->GetTemp(0).AsRegister<Register>();
383 Register base = isR6 ? ZERO : locations->InAt(0).AsRegister<Register>();
614 Register ref_reg = ref_.AsRegister<Register>();
654 DCHECK_EQ(entrypoint_.AsRegister<Register>(), T9);
655 __ Jalr(entrypoint_.AsRegister<Register>())
[all...] |
| code_generator_vector_mips64.cc | 61 __ FillB(dst, locations->InAt(0).AsRegister<GpuRegister>());
66 __ FillH(dst, locations->InAt(0).AsRegister<GpuRegister>());
70 __ FillW(dst, locations->InAt(0).AsRegister<GpuRegister>());
74 __ FillD(dst, locations->InAt(0).AsRegister<GpuRegister>());
866 GpuRegister base = locations->InAt(0).AsRegister<GpuRegister>();
882 GpuRegister index_reg = index.AsRegister<GpuRegister>();
[all...] |
| code_generator_vector_x86_64.cc | 56 __ movd(reg, locations->InAt(0).AsRegister<CpuRegister>());
64 __ movd(reg, locations->InAt(0).AsRegister<CpuRegister>());
70 __ movd(reg, locations->InAt(0).AsRegister<CpuRegister>());
75 __ movd(reg, locations->InAt(0).AsRegister<CpuRegister>()); // is 64-bit
865 return CodeGeneratorX86_64::ArrayAddress(base.AsRegister<CpuRegister>(), index, scale, offset);
893 __ testb(Address(locations->InAt(0).AsRegister<CpuRegister>(), count_offset), Immediate(1));
[all...] |
| code_generator_vector_mips.cc | 56 __ FillB(dst, locations->InAt(0).AsRegister<Register>());
61 __ FillH(dst, locations->InAt(0).AsRegister<Register>());
65 __ FillW(dst, locations->InAt(0).AsRegister<Register>());
862 Register base = locations->InAt(0).AsRegister<Register>();
878 Register index_reg = index.AsRegister<Register>();
[all...] |
| code_generator_vector_x86.cc | 59 __ movd(reg, locations->InAt(0).AsRegister<Register>());
67 __ movd(reg, locations->InAt(0).AsRegister<Register>());
73 __ movd(reg, locations->InAt(0).AsRegister<Register>());
872 return CodeGeneratorX86::ArrayAddress(base.AsRegister<Register>(), index, scale, offset);
900 __ testb(Address(locations->InAt(0).AsRegister<Register>(), count_offset), Immediate(1));
[all...] |
| locations.h | 181 T AsRegister() const {
|
| /art/compiler/utils/x86_64/ |
| managed_register_x86_64.cc | 63 Register low = AsRegisterPairLow().AsRegister();
64 Register high = AsRegisterPairHigh().AsRegister();
101 os << "CPU: " << static_cast<int>(AsCpuRegister().AsRegister());
|
| constants_x86_64.h | 34 constexpr Register AsRegister() const {
|
| assembler_x86_64.cc | 28 return os << reg.AsRegister();
[all...] |
| assembler_x86_64.h | 181 CHECK_EQ(base_in.AsRegister(), RSP);
212 CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode.
219 CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode.
[all...] |
| jni_macro_assembler_x86_64.cc | 52 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0);
129 cfi().Restore(DWARFReg(spill.AsCpuRegister().AsRegister()));
|
| assembler_x86_64_test.cc | 125 return a.AsRegister() < b.AsRegister();
[all...] |
| /external/v8/src/compiler/ |
| instruction-selector-impl.h | 145 location.AsRegister());
295 int reg_id = primary_location.AsRegister();
320 location.AsRegister(), virtual_register);
323 location.AsRegister(), virtual_register);
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| linkage.h | 145 int32_t AsRegister() const {
|
| /art/compiler/jni/quick/x86_64/ |
| calling_convention_x86_64.cc | 59 result |= (1 << r.AsX86_64().AsCpuRegister().AsRegister());
|
| /external/vixl/src/aarch32/ |
| instructions-aarch32.h | 161 Register AsRegister() const {
170 return os << reg.AsRegister();
[all...] |
| macro-assembler-aarch32.h | 681 return GetScratchRegisterList()->Includes(reg.AsRegister());
[all...] |
