/external/clang/test/CodeGen/ |
2003-09-18-BitfieldTests.c | 4 typedef struct BF { 8 } BF; 10 char *test1(BF *b) { 14 void test2(BF *b) { // Increment and decrement operators 19 void test3(BF *b) { 23 int test4(BF *b) { 27 void test5(BF *b, int i) { // array ref
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volatile.c | 23 struct { int x:3; } BF; 86 i=BF.x; 87 // CHECK-IT: load i8, i8* getelementptr {{.*}} @BF 88 // CHECK-MS: load i32, i32* getelementptr {{.*}} @BF 158 BF.x=i; 160 // CHECK-IT: load i8, i8* getelementptr {{.*}} @BF 161 // CHECK-MS: load i32, i32* getelementptr {{.*}} @BF 162 // CHECK-IT: store i8 {{.*}}, i8* getelementptr {{.*}} @BF 163 // CHECK-MS: store i32 {{.*}}, i32* getelementptr {{.*}} @BF
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
BlackfinInstrInfo.cpp | 30 : BlackfinGenInstrInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), 43 case BF::LOAD32fi: 44 case BF::LOAD16fi: 65 case BF::STORE32fi: 66 case BF::STORE16fi: 92 BuildMI(&MBB, DL, get(BF::JUMPa)).addMBB(TBB); 104 if (BF::ALLRegClass.contains(DestReg, SrcReg)) { 105 BuildMI(MBB, I, DL, get(BF::MOVE), DestReg) 110 if (BF::D16RegClass.contains(DestReg, SrcReg)) [all...] |
BlackfinRegisterInfo.cpp | 39 : BlackfinGenRegisterInfo(BF::RETS), Subtarget(st), TII(tii) {} 43 using namespace BF; 56 using namespace BF; 97 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg) 105 if (BF::PRegClass.contains(Reg)) { 106 assert(BF::PRegClass.contains(ScratchReg) && 108 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg) 112 assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register"); 113 assert(BF::DRegClass.contains(ScratchReg) && 115 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg [all...] |
BlackfinFrameLowering.cpp | 63 RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize); 69 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize); 79 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH)) 80 .addReg(BF::RETS, RegState::Kill); 81 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH)) 82 .addReg(BF::FP, RegState::Kill); 83 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP) 84 .addReg(BF::SP) [all...] |
BlackfinISelDAGToDAG.cpp | 88 return CurDAG->SelectNodeTo(N, BF::ADDpp, MVT::i32, TFI, 120 return BF::AnyCCRegClass.hasSubClassEq(RC); 124 return BF::DRegClass.hasSubClassEq(RC) || isCC(RC); 173 DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
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BlackfinRegisterInfo.h | 43 return &BF::PRegClass;
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BlackfinISelLowering.cpp | 46 setStackPointerRegisterToSaveRestore(BF::SP); 50 addRegisterClass(MVT::i32, BF::DRegisterClass); 51 addRegisterClass(MVT::i16, BF::D16RegisterClass); 186 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ? 187 BF::PRegisterClass : BF::DRegisterClass; 336 SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32); 429 unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB; 432 SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32 [all...] |
/external/valgrind/none/tests/ppc32/ |
test_dfp4.c | 93 * BF is the condition register bit field which can range from 0-7. But for 94 * testing purposes, we only use BF values of '0' and '5'. 96 static void _test_dtstdc(int BF, int DCM, dfp_val_t *val1, dfp_val_t *x1 __attribute__((unused))) 99 if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) { 100 fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM); 105 if (BF) 111 if (BF) 117 if (BF) 123 if (BF) [all...] |
test_dfp3.c | 165 static void _test_dcmpo(int BF, int x __attribute__((unused))) 167 if (BF < 0 || BF > 7) { 168 fprintf(stderr, "Invalid input to asm test: a=%d\n", BF); 171 switch (BF) { 201 static void _test_dcmpu(int BF, int x __attribute__((unused))) 203 if (BF < 0 || BF > 7) { 204 fprintf(stderr, "Invalid input to asm test: a=%d\n", BF); 207 switch (BF) { [all...] |
test_dfp5.c | 96 static void _test_dtstsf(unsigned int BF, unsigned int ref_sig, dfp_val_t *valB) 104 switch (BF) { 115 fprintf(stderr, "Invalid value %d for BF\n", BF); 120 static void _test_dtstsfq(unsigned int BF, unsigned int ref_sig, dfp_val_t *valB) 128 switch (BF) { 139 fprintf(stderr, "Invalid value %d for BF\n", BF); 551 int bf_idx, BF; 556 BF = BF_vals[bf_idx] [all...] |
/external/valgrind/none/tests/ppc64/ |
test_dfp4.c | 93 * BF is the condition register bit field which can range from 0-7. But for 94 * testing purposes, we only use BF values of '0' and '5'. 96 static void _test_dtstdc(int BF, int DCM, dfp_val_t *val1, dfp_val_t *x1 __attribute__((unused))) 99 if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) { 100 fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM); 105 if (BF) 111 if (BF) 117 if (BF) 123 if (BF) [all...] |
test_dfp3.c | 165 static void _test_dcmpo(int BF, int x __attribute__((unused))) 167 if (BF < 0 || BF > 7) { 168 fprintf(stderr, "Invalid input to asm test: a=%d\n", BF); 171 switch (BF) { 201 static void _test_dcmpu(int BF, int x __attribute__((unused))) 203 if (BF < 0 || BF > 7) { 204 fprintf(stderr, "Invalid input to asm test: a=%d\n", BF); 207 switch (BF) { [all...] |
test_dfp5.c | 96 static void _test_dtstsf(unsigned int BF, unsigned int ref_sig, dfp_val_t *valB) 104 switch (BF) { 115 fprintf(stderr, "Invalid value %d for BF\n", BF); 120 static void _test_dtstsfq(unsigned int BF, unsigned int ref_sig, dfp_val_t *valB) 128 switch (BF) { 139 fprintf(stderr, "Invalid value %d for BF\n", BF); 551 int bf_idx, BF; 556 BF = BF_vals[bf_idx] [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonGenExtract.cpp | 86 Value *BF = 0; 94 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), 101 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), 109 Match = match(In, m_And(m_Shl(m_Value(BF), m_ConstantInt(CSL)), 118 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)), 125 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)), 132 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), 139 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), 145 Type *Ty = BF->getType(); 203 Value *NewIn = IRB.CreateCall(ExtF, {BF, IRB.getInt32(W), IRB.getInt32(SR)}) [all...] |
/external/llvm/test/MC/MachO/ARM/ |
nop-thumb2-padding.s | 13 @ CHECK: 0000: 881800BF 00BF00BF 00BF00BF 00BF00BF |................|
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relax-thumb2-branches.s | 30 @ CHECK: 0100: 00000000 000000BF 7FDD0000 00000000 |................|
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/device/linaro/bootloader/edk2/OvmfPkg/SmmAccess/ |
SmmAccess2Dxe.inf | 22 FILE_GUID = AC95AD3D-4366-44BF-9A62-E4B29D7A2206
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/MCTargetDesc/ |
BlackfinMCTargetDesc.cpp | 42 InitBlackfinMCRegisterInfo(X, BF::RETS);
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/device/linaro/bootloader/edk2/ArmVirtPkg/VirtFdtDxe/ |
VirtFdtDxe.inf | 19 FILE_GUID = 9AD7DCB4-E6EC-472E-96BF-81C219A3F77E
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/external/spirv-llvm/lib/SPIRV/ |
SPIRVWriter.cpp | 106 foreachKernelArgMD(MDNode *MD, SPIRVFunction *BF, 110 SPIRVFunctionParameter *BA = BF->getArgument(I-1); 637 if (auto BF= getTranslatedValue(F)) 638 return static_cast<SPIRVFunction *>(BF); 642 SPIRVFunction *BF = static_cast<SPIRVFunction *>(mapValue(F, 644 BF->setFunctionControlMask(transFunctionControlMask(F)); 646 BM->setName(BF, F->getName()); 648 BM->addEntryPoint(ExecutionModelKernel, BF->getId()); 650 BF->setLinkageType(transLinkageType(F)); 655 SPIRVFunctionParameter *BA = BF->getArgument(ArgNo) [all...] |
SPIRVReader.cpp | 110 isOpenCLKernel(SPIRVFunction *BF) { 111 return BF->getModule()->isEntryPoint(ExecutionModelKernel, BF->getId()); 174 SPIRVFunction *BF, std::function<Metadata *(SPIRVFunctionParameter *)>Func){ 177 BF->foreachArgument([&](SPIRVFunctionParameter *Arg) { 458 Value *mapFunction(SPIRVFunction *BF, Function *F) { 459 SPIRVDBG(spvdbgs() << "[mapFunction] " << *BF << " -> "; 461 FuncMap[BF] = F; [all...] |
/cts/tools/vm-tests-tf/src/dot/junit/opcodes/aget_byte/d/ |
T_aget_byte_8.d | 27 .method public run([BF)B
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/external/v8/src/ppc/ |
code-stubs-ppc.h | 99 masm->instr_at_put(pos, (masm->instr_at(pos) & ~kBOfieldMask) | BF); 109 if (BF == (first_instruction & kBOfieldMask)) { 113 if (BF == (second_instruction & kBOfieldMask)) {
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assembler-ppc.h | 632 bc(b_offset, BF, encode_crbit(cr, CR_EQ), lk); 638 bc(b_offset, BF, encode_crbit(cr, CR_GT), lk); 644 bc(b_offset, BF, encode_crbit(cr, CR_LT), lk); 650 bc(b_offset, BF, encode_crbit(cr, CR_FU), lk); 656 bc(b_offset, BF, encode_crbit(cr, CR_SO), lk); 674 bclr(BF, encode_crbit(cr, CR_EQ), lk); 680 bclr(BF, encode_crbit(cr, CR_GT), lk); 686 bclr(BF, encode_crbit(cr, CR_LT), lk); 692 bclr(BF, encode_crbit(cr, CR_FU), lk); 698 bclr(BF, encode_crbit(cr, CR_SO), lk) [all...] |