OpenGrok
Home
Sort by relevance
Sort by last modified time
Full Search
Definition
Symbol
File Path
History
|
|
Help
Searched
refs:BIT10
(Results
1 - 25
of
125
) sorted by null
1
2
3
4
5
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsRcrb.h
47
#define B_PCH_RCRB_GCS_BBS (BIT11 |
BIT10
) // Boot BIOS Straps
PchRegsUsb.h
70
#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 |
BIT10
| BIT9) // Data Select
93
#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 |
BIT10
| BIT9)
PchRegsSata.h
67
#define B_PCH_SATA_COMMAND_INT_DIS
BIT10
// Interrupt Disable
85
#define B_PCH_SATA_PCISTS_DEV_STS_MASK (
BIT10
| BIT9) // DEVSEL# Timing Status
170
#define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 |
BIT10
| BIT9 | BIT8) // SATA Port Disable
175
#define B_PCH_SATA_PORT2_DISABLED
BIT10
191
#define B_PCH_SATA_PCS_PORT2_DET
BIT10
// Port 2 Present
PchRegsPcie.h
79
#define B_PCH_PCIE_SLCTL_SLSTS_PCC
BIT10
// Power Controller Control
PchRegsPcu.h
75
#define B_PCH_LPC_COMMAND_ID
BIT10
// Interrupt Disable
93
#define B_PCH_LPC_DEV_STS_DEVT_STS (
BIT10
| BIT9) // DEVSEL# Timing Status
200
#define B_PCH_LPC_FWH_BIOS_DEC_ED0
BIT10
// D0-D8 Enable
295
#define B_PCH_ILB_ULKMC_TRAPBY64R
BIT10
// SMI Caused by Port 64 Read
363
#define B_PCH_ILB_DXXIR_ICR_MASK (
BIT10
| BIT9 | BIT8) // INTC Mask
368
#define V_PCH_ILB_DXXIR_ICR_PIRQE
BIT10
// INTC Mapping to IRQ E
369
#define V_PCH_ILB_DXXIR_ICR_PIRQF (
BIT10
| BIT8) // INTC Mapping to IRQ F
370
#define V_PCH_ILB_DXXIR_ICR_PIRQG (
BIT10
| BIT9) // INTC Mapping to IRQ G
371
#define V_PCH_ILB_DXXIR_ICR_PIRQH (
BIT10
| BIT9 | BIT8) // INTC Mapping to IRQ H
426
#define B_PCH_ILB_DEF1_TPMPF
BIT10
// usb2leg_chknbit_TPM_PF
[
all
...]
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
35
#define B_EFI_MSR_FIXED_MTRR_ENABLE
BIT10
51
#define B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT
BIT10
/device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
PeCoffExtraActionLib.c
118
Dr7 = AsmReadDr7 () |
BIT10
; // H/w sets bit 10, some simulators don't
129
AsmWriteDr7 (
BIT10
);
158
NewDr7 = AsmReadDr7 () |
BIT10
; // H/w sets bit 10, some simulators don't
183
if (NewDr7 ==
BIT10
) {
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
Hi6220.h
32
#define CTRL4_PICO_VBUSVLDEXT
BIT10
45
#define CTRL5_PICOPHY_IDDIG
BIT10
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h
44
#define B_CMD_RESTART
BIT10
// 1 = IC_RESTART_EN
57
#define I2C_INTR_START_DET
BIT10
117
#define I2C_INTR_START_DET
BIT10
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h
27
#undef
BIT10
63
#define
BIT10
0x00000400U
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h
69
#define RXSTATUS_MCF
BIT10
// Frame has Multicast Address
84
#define TXSTATUS_NO_CA
BIT10
// Carrier signal not present during Tx (bad?)
110
#define INSTS_TDFO
BIT10
// Tx Data FIFO full
144
#define MPTCTRL_PHY_RST
BIT10
// Reset the PHY
205
#define MACCR_DISRTY
BIT10
// Disable Transmit Retry bit
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h
80
#define MCI_CLOCK_BYPASS
BIT10
93
#define MCI_STATUS_CMD_DATABLOCKEND
BIT10
146
#define MCI_CPSM_ENABLE
BIT10
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/
I2CLib.h
55
#define B_CMD_RESTART
BIT10
// 1 = IC_RESTART_EN
68
#define I2C_INTR_START_DET
BIT10
130
#define I2C_INTR_START_DET
BIT10
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530Dma.h
93
#define DMA4_CCR_WR_ACTIVE
BIT10
119
#define DMA4_CSR_SUPERVISOR_ERR
BIT10
Omap3530I2c.h
46
#define MST
BIT10
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
Isp1761UsbDxe.h
51
#define ISP1761_DC_INTERRUPT_EP0RX
BIT10
95
#define ISP1761_OTG_CTRL_OTG_DISABLE
BIT10
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Dma.h
93
#define DMA4_CCR_WR_ACTIVE
BIT10
119
#define DMA4_CSR_SUPERVISOR_ERR
BIT10
Omap3530I2c.h
46
#define MST
BIT10
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h
80
#define TCR_MON_CSN
BIT10
99
#define EPHSR_LOST_CARR
BIT10
130
#define CR_GPCNTRL
BIT10
205
#define RX_TOO_SHORT
BIT10
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h
72
BIT10
| BIT9 | BIT8 | BIT7)
VirtioBlk.h
62
#define VIRTIO_BLK_F_TOPOLOGY
BIT10
// information on optimal I/O alignment
VirtioNet.h
51
#define VIRTIO_NET_F_GUEST_UFO
BIT10
// guest can receive UFO
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
I2cRegs.h
57
#define B_I2C_REG_DATA_CMD_RESTART (
BIT10
) // Data Buffer and Command Register RESTART bit
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/
I2CLibPei.h
42
#define B_PCH_LPSS_I2C_STSCMD_INTRDIS
BIT10
// Interrupt Disable
97
#define B_CMD_RESTART
BIT10
// 1 = IC_RESTART_EN
110
#define I2C_INTR_START_DET
BIT10
174
#define I2C_INTR_START_DET
BIT10
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/
struct.s
35
BIT10
.field 10 ;
bit10
= 65
Completed in 224 milliseconds
1
2
3
4
5