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Searched
refs:BIT11
(Results
1 - 25
of
108
) sorted by null
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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsRcrb.h
47
#define B_PCH_RCRB_GCS_BBS (
BIT11
| BIT10) // Boot BIOS Straps
PchRegsUsb.h
70
#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 |
BIT11
| BIT10 | BIT9) // Data Select
93
#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 |
BIT11
| BIT10 | BIT9)
PchRegsSata.h
84
#define B_PCH_SATA_PCISTS_STA
BIT11
// Signaled Target-Abort Status
170
#define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 |
BIT11
| BIT10 | BIT9 | BIT8) // SATA Port Disable
174
#define B_PCH_SATA_PORT3_DISABLED
BIT11
190
#define B_PCH_SATA_PCS_PORT3_DET
BIT11
// Port 3 Present
PchRegsPcu.h
92
#define B_PCH_LPC_DEV_STS_STA
BIT11
// Signaled Target Abort
199
#define B_PCH_LPC_FWH_BIOS_DEC_ED8
BIT11
// D8-DF Enable
294
#define B_PCH_ILB_ULKMC_TRAPBY64W
BIT11
// SMI Caused by Port 64 Write
467
#define B_PCH_ACPI_PM1_STS_PRBTNOR
BIT11
// Power Button Override Status
501
#define B_PCH_ACPI_PM1_CNT_SLP_TYP (BIT12 |
BIT11
| BIT10) // Sleep Type
[
all
...]
PchRegsSpi.h
78
#define B_PCH_SPI_OPTYPE5_MASK (
BIT11
| BIT10) // Opcode Type 5 Mask
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
33
#define B_EFI_MSR_CACHE_MTRR_VALID
BIT11
34
#define B_EFI_MSR_GLOBAL_MTRR_ENABLE
BIT11
50
#define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT
BIT11
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h
81
#define TCR_FDUPLX
BIT11
100
#define EPHSR_EXC_DEF
BIT11
124
#define RPCR_ANEG
BIT11
143
#define CTR_AUTO_REL
BIT11
177
#define PTR_NOT_EMPTY
BIT11
206
#define RX_TOO_LONG
BIT11
248
#define PHYCR_PD
BIT11
// Power-Down switch
261
#define PHYSTS_10BASET_HDPLX
BIT11
// 10Mbps Half-Duplex ability
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h
28
#undef
BIT11
64
#define
BIT11
0x00000800U
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h
70
#define RXSTATUS_RUNT
BIT11
// Bad frame
85
#define TXSTATUS_LOST_CA
BIT11
// Lost carrier during Tx
151
#define PHYCR_PD
BIT11
// Power-Down switch
164
#define PHYSTS_10BASET_HDPLX
BIT11
// 10Mbps Half-Duplex ability
206
#define MACCR_BCAST
BIT11
// Disable Broadcast Frames bit
268
#define MII_ACC_PHY_VALUE
BIT11
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h
81
#define MCI_CLOCK_WIDEBUS
BIT11
94
#define MCI_STATUS_CMD_ACTIVE
BIT11
129
#define MCI_CLR_ALL_STATUS (
BIT11
- 1)
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530Prcm.h
109
#define CM_FCLKEN_PER_EN_UART3_ENABLE
BIT11
134
#define CM_ICLKEN_PER_EN_UART3_ENABLE
BIT11
/device/linaro/bootloader/edk2/MdePkg/Library/BasePeCoffLib/Arm/
PeCoffLoaderEx.c
48
Address |= (((Movt & BIT26) != 0) ?
BIT11
: 0); // i
69
Patch |= (((Address &
BIT11
) != 0) ? BIT10 : 0); // i
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Prcm.h
109
#define CM_FCLKEN_PER_EN_UART3_ENABLE
BIT11
134
#define CM_ICLKEN_PER_EN_UART3_ENABLE
BIT11
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h
56
#define I2C_INTR_GEN_CALL
BIT11
// General call received
116
#define I2C_INTR_GEN_CALL
BIT11
// General call received
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
Hi6220.h
33
#define CTRL4_PICO_VBUSVLDEXTSEL
BIT11
/device/linaro/bootloader/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/
BeagleBoard.c
48
MmioWrite32(GPIO6_BASE + GPIO_OE, (OldPinDir |
BIT11
| BIT12 | BIT13));
/device/linaro/bootloader/edk2/BeagleBoardPkg/Library/BeagleBoardLib/
BeagleBoard.c
48
MmioWrite32(GPIO6_BASE + GPIO_OE, (OldPinDir |
BIT11
| BIT12 | BIT13));
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h
71
#define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 |
BIT11
| \
VirtioNet.h
52
#define VIRTIO_NET_F_HOST_TSO4
BIT11
// host can receive TSOv4
/device/linaro/bootloader/edk2/ShellPkg/Include/Library/
HandleParsingLib.h
153
#define HR_CHILD_HANDLE
BIT11
154
#define HR_VALID_MASK (BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7|BIT8|BIT9|BIT10|
BIT11
)
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/
I2CLib.h
67
#define I2C_INTR_GEN_CALL
BIT11
// General call received
129
#define I2C_INTR_GEN_CALL
BIT11
// General call received
/device/linaro/bootloader/edk2/MdePkg/Library/BasePrintLib/
PrintLibInternal.h
34
#define PRECISION
BIT11
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
CommonIncludes.h
105
#define
BIT11
0x00000800
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
QuarkNcSocId.h
291
#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 |
BIT11
| BIT10 | BIT9 | BIT8)
464
#define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+
BIT11
+BIT10)
649
#define B_QNC_PCIE_DCAP_E1AL (
BIT11
| BIT10 | BIT9) // L1 Acceptable exit latency
660
#define B_QNC_PCIE_LCAP_APMS_MASK (
BIT11
| BIT10) //Active state link PM support mask
667
#define B_QNC_PCIE_LSTS_LT (
BIT11
) //Link training
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all
...]
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/
ThumbDisassembler.c
598
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1,
BIT11
));
715
Target |= ((OpCode32 &
BIT11
) ==
BIT11
)? BIT19 : 0; // J2
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...]
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