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Searched
refs:BIT12
(Results
1 - 25
of
106
) sorted by null
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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsUsb.h
70
#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (
BIT12
| BIT11 | BIT10 | BIT9) // Data Select
93
#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (
BIT12
| BIT11 | BIT10 | BIT9)
PchRegsPcie.h
78
#define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE
BIT12
// Data Link Layer State Changed Enable
PchRegsSata.h
83
#define B_PCH_SATA_PCISTS_RTA
BIT12
// Received Target-Abort Status
170
#define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 |
BIT12
| BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable
173
#define B_PCH_SATA_PORT4_DISABLED
BIT12
189
#define B_PCH_SATA_PCS_PORT4_DET
BIT12
// Port 4 Present
PchRegsSpi.h
77
#define B_PCH_SPI_OPTYPE6_MASK (BIT13 |
BIT12
) // Opcode Type 6 Mask
97
#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 |
BIT12
) // Flash Descriptor Section Select
PchRegsPcu.h
91
#define B_PCH_LPC_DEV_STS_RTA
BIT12
// Received Target Abort
198
#define B_PCH_LPC_FWH_BIOS_DEC_EE0
BIT12
// E0-E8 Enable
353
#define B_PCH_ILB_DXXIR_IDR_MASK (BIT14 | BIT13 |
BIT12
) // INTD Mask
355
#define V_PCH_ILB_DXXIR_IDR_PIRQB
BIT12
// INTD Mapping to IRQ B
357
#define V_PCH_ILB_DXXIR_IDR_PIRQD (BIT13 |
BIT12
) // INTD Mapping to IRQ D
359
#define V_PCH_ILB_DXXIR_IDR_PIRQF (BIT14 |
BIT12
) // INTD Mapping to IRQ F
361
#define V_PCH_ILB_DXXIR_IDR_PIRQH (BIT14 | BIT13 |
BIT12
) // INTD Mapping to IRQ H
394
#define B_PCH_ILB_OIC_SIRQEN
BIT12
// Serial IRQ Enable
501
#define B_PCH_ACPI_PM1_CNT_SLP_TYP (
BIT12
| BIT11 | BIT10) // Sleep Type
[
all
...]
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530Usb.h
26
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
BIT12
Omap3530Dma.h
96
#define DMA4_CCR_SRC_AMODE_POST_INC (0 |
BIT12
)
98
#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 |
BIT12
)
121
#define DMA4_CSR_DRAIN_END
BIT12
Omap3530I2c.h
28
#define BB
BIT12
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h
82
#define TCR_STP_SQET
BIT12
101
#define EPHSR_CTR_ROL
BIT12
125
#define RPCR_DPLX
BIT12
131
#define CR_NO_WAIT
BIT12
146
#define CTR_RESERVED (
BIT12
| BIT9 | BIT4)
207
#define RX_ODD_FRAME
BIT12
217
#define PCW_CRC
BIT12
249
#define PHYCR_AUTO_EN
BIT12
// Auto-Negotiation Enable
262
#define PHYSTS_10BASET_FDPLX
BIT12
// 10Mbps Full-Duplex ability
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Usb.h
26
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
BIT12
Omap3530Dma.h
96
#define DMA4_CCR_SRC_AMODE_POST_INC (0 |
BIT12
)
98
#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 |
BIT12
)
121
#define DMA4_CSR_DRAIN_END
BIT12
Omap3530I2c.h
28
#define BB
BIT12
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h
71
#define RXSTATUS_LE
BIT12
// Actual length of frame different than it claims
97
#define IRQCFG_IRQ_INT
BIT12
// State of internal interrupts line
145
#define MPTCTRL_PM_MODE_MASK (
BIT12
| BIT13) // Set the power mode
152
#define PHYCR_AUTO_EN
BIT12
// Auto-Negotiation Enable
165
#define PHYSTS_10BASET_FDPLX
BIT12
// 10Mbps Full-Duplex ability
196
#define PHYSSCS_AUTODONE
BIT12
// Auto-Negotiation Done
207
#define MACCR_LCOLL
BIT12
// Late Collision Control bit
310
#define TX_CMD_A_LAST_SEGMENT
BIT12
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
49
#define B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT
BIT12
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h
29
#undef
BIT12
65
#define
BIT12
0x00001000U
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h
36
#define IC_TAR_10BITADDR_MASTER
BIT12
112
#define IC_TAR_10BITADDR_MASTER
BIT12
/device/linaro/bootloader/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/
BeagleBoard.c
48
MmioWrite32(GPIO6_BASE + GPIO_OE, (OldPinDir | BIT11 |
BIT12
| BIT13));
/device/linaro/bootloader/edk2/BeagleBoardPkg/Library/BeagleBoardLib/
BeagleBoard.c
48
MmioWrite32(GPIO6_BASE + GPIO_OE, (OldPinDir | BIT11 |
BIT12
| BIT13));
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h
71
#define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 |
BIT12
| BIT11 | \
VirtioNet.h
53
#define VIRTIO_NET_F_HOST_TSO6
BIT12
// host can receive TSOv6
/device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/
AArch64Mmu.h
51
#define TT_ALIGNMENT_BLOCK_ENTRY
BIT12
52
#define TT_ALIGNMENT_DESCRIPTION_TABLE
BIT12
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/
I2CLib.h
47
#define IC_TAR_10BITADDR_MASTER
BIT12
125
#define IC_TAR_10BITADDR_MASTER
BIT12
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
UhciReg.h
58
#define USBPORTSC_SUSP
BIT12
// Suspend
/device/linaro/bootloader/edk2/MdePkg/Library/BasePrintLib/
PrintLibInternal.h
35
#define ARGUMENT_REVERSED
BIT12
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
CommonIncludes.h
104
#define
BIT12
0x00001000
Completed in 2455 milliseconds
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